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參數(shù)資料
| 型號： | CY28410ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CK410GRANTSDALE 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 266MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | SLCY28410ZXCT |
CY28410
........................Document #: 38-07593 Rev. *C Page 5 of 17
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
1
DOT_96T/C
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
5
1
USB_48
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
4
1
REF
REF Output Enable
0 = Disabled, 1 = Enabled
3
0
Reserved
2
1
CPU[T/C]1
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
1
CPU[T/C]0
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
0
CPUT/C
SRCT/C
PCIF
PCI
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
1
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
5
1
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
4
1
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
3
1
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
2
1
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
1
PCIF2
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
0
1
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
6
0
SRC6
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
5
0
SRC5
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
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