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參數(shù)資料
| 型號： | CY28410ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Coaxial Cable; Impedance:75ohm; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 266 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 281K |
| 代理商： | CY28410ZXCT |
CY28410
Document #: 38-07593 Rev. *C
Page 8 of 18
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tance loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce
= 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
(
)
1
=
CLe
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