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參數(shù)資料
| 型號： | CY28410ZXCT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Coaxial Cable; Impedance:75ohm; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes |
| 中文描述： | 266 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 281K |
| 代理商： | CY28410ZXCT |
CY28410
Document #: 38-07593 Rev. *C
Page 6 of 18
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Reserved, Set = 0
0
0
Reserved
Byte 4: Control Register 4
Bit
7
6
@Pup
0
0
Name
Reserved
DOT96[T/C]
Description
Reserved, Set = 0
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
5
0
PCIF2
4
0
PCIF1
3
0
PCIF0
2
1
0
1
1
1
Reserved
Reserved
Reserved
Byte 5: Control Register 5
Bit
7
@Pup
0
Name
Description
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
6
5
4
3
0
0
0
0
Reserved
Reserved
Reserved
SRC[T/C][7:0]
2
0
CPU[T/C]2
1
0
CPU[T/C]1
0
0
CPU[T/C]0
Byte 6: Control Register 6
Bit
7
@Pup
0
Name
Description
REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
Reserved, Set = 0
REF Output Drive Strength
0 = Low, 1 = High
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6
0
5
4
0
1
Reserved
REF
3
1
PCIF, SRC, PCI
Byte 3: Control Register 3
(continued)
Bit
@Pup
Name
Description
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