參數(shù)資料
型號(hào)： CY28410ZXCT
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： XO, clock
英文描述： Coaxial Cable; Impedance:75ohm; Conductor Size AWG:30; No. Strands x Strand Size:7 x 38; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes
中文描述： 266 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝： 6 X 12 MM, LEAD FREE, MO-153, TSSOP2-56
文件頁(yè)數(shù)： 2/18頁(yè)
文件大?。?/td> 281K
代理商： CY28410ZXCT
CY28410
Document #: 38-07593 Rev. *C
Page 2 of 18
Pin Definitions
Pin No.
44,43,41,40
36,35
Name
Type
O, DIF
Differential CPU clock outputs
.
O, DIF
Selectable Differential CPU or SRC clock output
.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
O, DIF
Fixed 96-MHz clock output
.
I
3.3V tolerant input for CPU frequency selection
.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z,1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
I
3.3V tolerant input for CPU frequency selection
.
Selects test mode if pulled
to V
IHFS_C
when VTT_PWRGD# is asserted low.
Refer to DC Electrical Specifications table for
V
ILFS_C
,V
IMFS_C
,V
IHFS_C
specifi-
cations.
I
A Precision resistor is attached to this pin, which is connected to the internal
current reference.
O, SE
33-MHz clocks
.
O, SE
33-MHz clocks
.
I/O, SE
33-MHz clock/CPU2 select
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC7
O, SE
Reference clock
. 3.3V 14.318 MHz clock output.
I
SMBus-compatible SCLOCK
.
I/O
SMBus-compatible SDATA
.
O, DIF
Differential serial reference clock
. recommended output for SATA.
Description
CPUT/C
CPUT2_ITP/SRCT7,
CPUC2_ITP/SRCC7
14,15
18
DOT96T, DOT96C
FS_A
16
FS_B/TEST_MODE
53
FS_C/TEST_SEL
39
IREF
54,55,56,3,4,5 PCI
9,10
8
PCIF
PCIF0/ITP_EN
52
46
47
26,27
REF
SCLK
SDATA
SRC4_SATAT,
SRC4_SATAC
SRCT/C
19,20,22,23,2
4,25,31,30,33,
32
12
11
42
1,7
48
21,28,34
37
13
45
2,6
51
29
38
17
O, DIF
Differential serial reference clocks
.
USB_48
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
I/O, SE
Fixed 48 MHz clock output.
PWR
3.3V power supply for outputs
.
PWR
3.3V power supply for outputs
.
PWR
3.3V power supply for outputs
.
PWR
3.3V power supply for outputs
.
PWR
3.3V power supply for outputs
.
PWR
3.3V power supply for PLL
.
GND
Ground for outputs
.
GND
Ground for outputs
.
GND
Ground for outputs
.
GND
Ground for outputs
.
GND
Ground for outputs
.
GND
Ground for PLL
.
I, PU
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a realtime input for asserting
power-down (active high)
I
14.318-MHz Crystal Input
O, SE
14.318-MHz Crystal Output
50
49
XIN
XOUT
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