參數(shù)資料
型號: CY28405OXCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: CK409-Compliant Clock Synthesizer
中文描述: 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: LEAD FREE, SSOP-48
文件頁數(shù): 8/19頁
文件大?。?/td> 259K
代理商: CY28405OXCT
CY28405
Document #: 38-07512 Rev. *B
Page 8 of 19
Byte 8: Control Register 8
Bit
7
6
5
@Pup
0
1
1
Name
Description
CPU
PCIF
PCI
3V66
Spread Spectrum Selection
‘000’ = ±0.20% triangular
‘001’ = + 0.12, – 0.62%
‘010’ = + 0.25, – 0.75%
‘011’ = –0.05, – 0.45% triangular
‘100’ = ± 0.25%
‘101’ = + 0.00, – 0.50%
‘110’ = ± 0.5%
‘111’ = ± 0.38%
SW Frequency selection bits. See
Table 1
.
4
3
2
1
0
0
0
0
0
0
FSEL_4
FSEL_3
FSEL_2
FSEL_1
FSEL_0
Byte 9: Control Register 9
Bit
7
@Pup
0
Name
Description
PCIF
PCIF Clock Output Drive Strength Control
0 = Low Drive strength, 1 = High Drive strength
PCI Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
3V66 Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
REF Clock Output Drive Strength
0 = Low Drive strength, 1 = High Drive strength
Reserved
Reserved
Vendor Test Mode (always program to 0)
Vendor Test Mode (always program to 0)
6
0
PCI
5
0
3V66
4
1
REF
3
2
1
0
1
1
0
0
Reserved
Reserved
Reserved
Reserved
Byte 10: Control Register 10
Bit
7
6
@Pup
0
0
Name
Description
PCI_Skew1
PCI_Skew0
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
5
4
0
0
3V66_Skew1
3V66_Skew0
3
2
1
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
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