參數(shù)資料
型號: CY28405OXCT
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: CK409-Compliant Clock Synthesizer
中文描述: 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: LEAD FREE, SSOP-48
文件頁數(shù): 7/19頁
文件大?。?/td> 259K
代理商: CY28405OXCT
CY28405
Document #: 38-07512 Rev. *B
Page 7 of 19
Byte 5: Control Register 5
Bit
7
@Pup
1
Name
Description
DOT_48
DOT_48 Output Enable
0 = Disabled, 1 = Enabled
Reserved
3V66_3/VCH/SELVCH Frequency Select
0 = 3V66 mode, 1 = VCH (48MHz) mode
May be written to override the power-up value.
3V66_3/VCH/SELVCH Output Enable
0 = Disabled,1 = Enabled
Reserved
3V66_2 Output Enable
0 = Disabled, 1 = Enabled
3V66_1 Output Enable
0 = Disabled, 1 = Enabled
3V66_0 Output Enable
0 = Disabled, 1 = Enabled
6
5
1
Reserved
3V66_3/VCH/SELVCH
HW
4
1
3V66_3/VCH/SELVCH
3
2
1
1
Reserved
3V66_2
1
1
3V66_1
0
1
3V66_0
Byte 6: Control Register 6
Bit
7
@Pup
0
Name
Description
REF
PCIF
PCI
3V66
3V66_3/VCH/SELVCH
USB_48
DOT_48
CPUT, CPUT_ITP
CPUC,CPUC_ITP
Reserved
Reserved
Reserved
Reserved
PCIF
PCI
3V66
CPUT,CPUT_ITP
CPUC,CPUC_ITP
REF_1
Test Clock Mode
0 = Disabled, 1 = Enabled
When Test Clock Mode is enabled, the FS_A/REF_0 pin reverts to a
dedicated FS_A input, allowing asynchronous selection between Hi-Z and
REF/N mode.
6
5
4
3
2
0
0
0
0
0
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
Reserved, Set = 0
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
REF_0 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
Byte 7: Vendor ID
Bit
@Pup
0
1
0
0
1
0
0
0
Name
Description
7
6
5
4
3
2
1
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
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