參數(shù)資料
型號(hào)： CY28405OXCT
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： CK409-Compliant Clock Synthesizer
中文描述： 200.9 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： LEAD FREE, SSOP-48
文件頁(yè)數(shù)： 3/19頁(yè)
文件大小： 259K
代理商： CY28405OXCT
CY28405
Document #: 38-07512 Rev. *B
Page 3 of 19
MODE Select
The hardware strapping MODE input pin can be used to select
the functionality of the RESET#/PD# pin. The default (internal
pull up) configuration is for this pin to function as a RESET#
Watchdog output. When pulled LOW during device power-up,
the RESET#/PD# pin will be configured to function as a Power
Down input pin.
Frequency Select Pins
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A through FS_E inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A through FS_E input values. For all logic
levels of FS_A through FS_E, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#
and FS_A through FS_E transitions will be ignored.
Table 1. Frequency Selection Table
Input Conditions
FS_D
FS_C
FSEL_3
FSEL_2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Output Frequency
VCO Freq.
805.6
801.6
864.0
809.6
Reserved
Reserved
Reserved
Reserved
754.2
781.6
801.6
805.2
807.0
888.0
Reserved
Reserved
Reserved
Reserved
669.6
680.0
700.0
720.0
740.0
760.0
807.2
803.4
803.6
Reserved
800.0
800.0
800.0
Reserved
PLL Gear
Constants
(G)
24004009.32
24004009.32
24004009.32
24004009.32
Reserved
Reserved
Reserved
Reserved
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
32005345.76
Reserved
Reserved
Reserved
Reserved
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
48008018.65
24004009.32
32005345.76
48008018.65
Reserved
24004009.32
32005345.76
48008018.65
Reserved
FS_E
FSEL_4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS_B
FSEL_1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS_A
FSEL_0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
100.7
100.2
108.0
101.2
Reserved
Reserved
Reserved
Reserved
125.7
130.3
133.6
134.2
134.5
148.0
Reserved
Reserved
Reserved
Reserved
167.4
170.0
175.0
180.0
185.0
190.0
100.9
133.9
200.9
Reserved
100.0
133.3
200.0
Reserved
3V66
67.1
66.8
72.0
67.5
Reserved
Reserved
Reserved
Reserved
62.9
65.1
66.8
67.1
67.3
74.0
Reserved
Reserved
Reserved
Reserved
55.8
56.7
58.3
60.0
61.7
63.3
67.3
67.0
67.0
Reserved
66.7
66.7
66.7
Reserved
PCI
33.6
33.4
36.0
33.7
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Reserved
Reserved
Reserved
Reserved
31.4
32.6
33.4
33.6
33.6
37.0
Reserved
Reserved
Reserved
Reserved
27.9
28.3
29.2
30.0
30.8
31.7
33.6
33.5
33.5
Reserved
33.3
33.3
33.3
Reserved
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