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參數(shù)資料
| 型號： | CY28405 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CK409-Compliant Clock Synthesizer |
| 中文描述： | CK409兼容的時鐘合成器 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 259K |
| 代理商： | CY28405 |
CY28405
Document #: 38-07512 Rev. *B
Page 9 of 19
Byte 11: Control Register 11
Bit
7
6
@Pup
0
0
Name
Description
Reserved
Recovery_Frequency
Vendor Test Mode (always program to 0)
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use Hardware settings
1: Use Last SW table Programmed values
To enable this function the register bit must first be set to “0” before toggling
to “1”.
0: Do not reload
1: Reset timer but continue to count.
This bit is set to “1” when the Watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp
Watchdog timer time stamp selection:
0000: Off
0001: 2 second
0010: 4 seconds
0011: 6 seconds
.
.
.
1110: 28seconds
1111: 30seconds
5
0
Watchdog Time Stamp
Reload
4
0
WD_Alarm
3
2
1
0
0
0
0
0
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
Byte 12: Control Register 12
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Description
CPU_FSEL_N8
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Byte 13: Control Register 13
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Description
CPU_FSEL_N0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
If Prog_Freq_EN is set, the values programmed in CPU_FSEL_N[8:0] and
CPU_FSEL_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the SEL[4:0] register will be used.
Byte 14: Control Register 14
Bit
7
@Pup
0
Name
Description
FS_(E:A)
FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL(4:0) settings
Reserved, Set = 1
Reserved, Set = 0
6
5
1
0
Reserved
Reserved
相關PDF資料 |
PDF描述 |
|---|---|
| CY28405OXCT | CK409-Compliant Clock Synthesizer |
| CY28405OC | CK409-Compliant Clock Synthesizer |
| CY28405OCT | Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-6 |
| CY28405OXC | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:8; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
| CY28408 | Clock Synthesizer with Differential CPU Outputs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY28405-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405-3 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28405OC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC-2T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 865 AND 875 CHIPSETS (CK409) - Bulk |
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