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參數(shù)資料
| 型號： | CY28405 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CK409-Compliant Clock Synthesizer |
| 中文描述： | CK409兼容的時鐘合成器 |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 259K |
| 代理商： | CY28405 |
CY28405
Document #: 38-07512 Rev. *B
Page 5 of 19
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
1
2:8
9
10
11:18
Description
Bit
1
2:8
9
10
11:18
Description
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation, bits[6:0]
of the command code represents the offset of
the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
19
19
20
20:27
28
29
21:27
28
29
30:37
38
39
Byte 0: Control Register 0
Bit
7
6
@Pup
0
1
Name
Description
Reserved, Set= 0
PCI Drive Strength Override
0 = Force All PCI and PCIF Outputs to Low Drive Strength
1= Force All PCI and PCIF Outputs to High Drive Strength
Reserved, Set= 0
Power up latched value of FS_E pin
Power up latched value of FS_D pin
Power up latched value of FS_C pin
Power up latched value of FS_B pin
Power up latched value of FS_A pin
PCIF
PCI
5
4
3
2
1
0
0
Reserved
FS_E
FS_D
FS_C
FS_B
FS_A
HW
HW
HW
HW
HW
Byte 1: Control Register 1
Bit
7
6
5
4
3
2
@Pup
0
1
1
1
1
1
Name
Description
Reserved
Reserved
Reserved
Reserved
Reserved
CPUT_ITP, CPUC_ITP
Reserved, set = 0
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
Reserved, set = 1
CPUT/C_ITP Output Enable
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)1 Output Enable,
0 = Disabled (three-state), 1 = Enabled
CPU(T/C)0 Output Enable
0 = Disabled (three-state), 1 = Enabled
1
1
CPUT1, CPUC1
0
1
CPUT0, CPUC0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28405OXCT | CK409-Compliant Clock Synthesizer |
| CY28405OC | CK409-Compliant Clock Synthesizer |
| CY28405OCT | Circular Connector; No. of Contacts:6; Series:; Body Material:Aluminum; Connecting Termination:Solder; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-6 |
| CY28405OXC | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:8; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
| CY28408 | Clock Synthesizer with Differential CPU Outputs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28405-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405-3 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC | 制造商:Cypress Semiconductor 功能描述: |
| CY28405OC-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28405OC-2T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL 865 AND 875 CHIPSETS (CK409) - Bulk |
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