參數(shù)資料
型號(hào): CY28405
廠商: Cypress Semiconductor Corp.
英文描述: CK409-Compliant Clock Synthesizer
中文描述: CK409兼容的時(shí)鐘合成器
文件頁(yè)數(shù): 17/19頁(yè)
文件大小: 259K
代理商: CY28405
CY28405
Document #: 38-07512 Rev. *B
Page 17 of 19
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Table 9. Maximum Lumped Capacitive Output Loads
Clock
PCI Clocks
3V66 Clocks
USB Clock
DOT Clock
REF Clock
Max Load
30
30
20
10
30
Units
pF
pF
pF
pF
pF
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
50 Ohms
Reference R, I
REF
– V
DD
(3*R
REF
)
R
REF
= 475 1%, I
REF
= 2.32 mA
Output Current
I
OH
= 6*I
REF
V
OH
@ Z
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
Commercial, 0
°
to 70
°
C
Commercial, 0
°
to 70
°
C
CY28405OC
CY28405OCT
Lead Free
CY28405OXC
CY28405OXCT
48-pin Shrunk Small Outline package (SSOP)
48-pin Shrunk Small Outline package (SSOP) – Tape and Reel
48-pin Shrunk Small Outline package (SSOP)
48-pin Shrunk Small Outline package (SSOP) – Tape and Reel
Commercial, 0
°
to 70
°
C
Commercial, 0
°
to 70
°
C
CPUT
T
PCB
T
PCB
CPUC
33
33
49.9
49.9
Measurement
Point
2pF
475
IREF
Measurement
Point
2pF
Figure 7. 0.7V Load Configuration
2.4V
0.4V
3.3V
0V
T r
T f
1.5V
3.3V signals
tD C
Probe
O utput under T est
Load C ap
-
-
Figure 8. Lumped Load For Single-Ended Output Signals (for AC Parameter Measurement)
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