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參數(shù)資料
| 型號(hào)： | CY28346ZCT |
| 廠(chǎng)商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Clock Synthesizer with Differential CPU Outputs |
| 中文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6 X 12 MM, MO-153, TSSOP2-56 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大?。?/td> | 179K |
| 代理商： | CY28346ZCT |
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CY28346
Document #: 38-07331 Rev. *B
Page 8 of 20
Iout is selectable depending on implementation. The param-
eters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the
host swing select functions table. For all configurations, the
deviation from the expected output current is ±7% as shown in
the current accuracy table.
USB and DOT 48M Phase Relationship
The 48MUSB and 48MDOT clocks are in phase. It is under-
stood that the difference in edge rate will introduce some
inherent offset. When 3V66_1/VCH clock is configured for
VCH (48-MHz) operation it is also in phase with the USB and
DOT outputs. See
Figure 5
.
66IN to 66B(0:2) Buffered Prop Delay
The 66IN to 66B(0:2) output delay is shown in
Figure 6
.
The Tpd is the prop delay from the input pin (66IN) to the
output pins (66B[0:2]). The outputs
’
variation of Tpd is
described in the AC parameters section of this data sheet. The
measurement taken at 1.5V.
66B(0:2) to PCI Buffered Clock Skew
Figure 7
shows the difference (skew) between the 3V33(0:5)
outputs when the 66M clocks are connected to 66IN. This
offset is described in the Group Timing Relationship and Toler-
ances section of this data sheet. The measurements were
taken at 1.5V.
3V66 to PCI Un-Buffered Clock Skew
Figure 8
shows the timing relationship between 3V66(0:5) and
PCI(0:6) and PCI_F(0:2) when configured to run in the unbuf-
fered mode.
Table 5. CPU Clock Current Select Function
Mult0
0
1
Board Target Trace/Term Z
50
50
Reference R, Iref
–
Vdd (3*Rr)
Rr = 221 1%, Iref = 5.00mA
Rr = 475 1%, Iref = 2.32mA
Output Current
Ioh = 4*Iref
Ioh = 6*Iref
Voh @ Z
1.0V @ 50
0.7V @ 50
Table 6. Group Timing Relationship and Tolerances
Description
Offset
2.5 ns
0.0 ns
2.5 ns
Tolerance
±
1.0 ns
±
1.0 ns
±
1.0 ns
Conditions
3V66 to PCI
48MUSB to 48MDOT Skew
66B(0:2) to PCI offset
3V66 Leads PCI (unbuffered mode)
0 degrees phase shift
66B Leads PCI (buffered mode)
48MUSB
48MDOT
Figure 5. 48MUSB and 48MDOT Phase Relationship
66IN
66B(0:2)
Tpd
Figure 6. 66IN to 66B(0:2) Output Delay Figure
66B(0:2)
PCI(0:6)
PCIF(0:2)
1.5-
3.5ns
Figure 7. Buffer Mode
–
33V66(0:1); 66BUF(0:2) Phase Relationship
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PDF描述 |
|---|---|
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| CY28347ZCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OC | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
| CY28347OCT | Universal Single-chip Clock Solution for VIA P4M266/KM266 DDR Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28346ZI-2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB clk for Intel 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZI-2T | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB clk for Intel 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXC-2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CY28346ZXC-2T | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 NB Clk Intel Brkdale 830M & 845 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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