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參數(shù)資料
| 型號(hào)： | CY28326 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FTG for VIA PT880 Serial Chipset |
| 中文描述： | FTG的威盛PT880系列芯片組 |
| 文件頁數(shù)： | 8/23頁 |
| 文件大?。?/td> | 288K |
| 代理商： | CY28326 |
CY28326
Document #: 38-07616 Rev. *A
Page 8 of 23
6
0
Test bit
Don’t change, Default =0
5
0
Test bit
Don’t change, Default =0
4
3
2
1
0
0
1
0
0
0
Reserved
Reserved
Reserved
Fract_Align1
Fract_Align0
Reserved
Reserved
Reserved
AGP and PCI fixed frequency selection bit 1
AGP and PCI fixed frequency. This option does not incorporate spread
spectrum. It is enabled through Fixed_AGP_SEL bits (B8b7)
Fract_align1
0
0
1
1
Fract_align1
0
1
0
1
AGP
66.6
75.0
75.0
85.7
PCI
33.3
37.5
37.5
42.8
Byte 8: Control Register
Bit
7
@Pup
0
Name/Pin Affected
AGP
Description
AGP output frequency select mode. Selects the frequency source for AGP
outputs.
0 = Set according to Frequency Selection Table
1 = Set according to Fractional Aligner Settings Program Fract Aligner
values before setting this bit.
Reserved
This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted.
0 = Use hardware settings, 1 = use last SW table programmed values.
This bit is set to “1” when the watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp.
Watchdog timer time stamp selection:
0000: Off
0001: 10msec
0010: 4 second
.
.
.
1110: 28 seconds
1111: 30 seconds
6
5
1
0
Reserved
Recovery_Frequency
4
0
WD_Alarm
3
2
1
0
0
0
0
0
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
Byte 9: Control Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name/Pin Affected
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
Description
If Dial-A-Frequency Enable bit is set, the values programmed in
CPU_FSEL_N[8:0] and CPU_FSEL_M[6:0] will be used to determine the
CPU output frequency.
This setting of the FS_Override bit determines the frequency ratio for CPU
and other output clocks. When it is cleared, the same frequency ratio
stated in the latched FS[D:A] register will be used. When it is set, the
frequency ratio stated in the SEL[3:0] register will be used.
Byte 7: Fract Aligner Control Register
(continued)
Bit
@Pup
Name/Pin Affected
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28326OC | FTG for VIA PT880 Serial Chipset |
| CY28326OCT | FTG for VIA PT880 Serial Chipset |
| CY28326OXC | Single Pole Normally Open: 1-Form-A |
| CY28326OXCT | Single Pole Normally Open: 1-Form-A |
| CY28341-2 | Universal Clock Chip for VIA P4M/KT/KM400 DDR Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28326OC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326OXC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28326OXCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for VIA PT880 Serial Chipset |
| CY28326SPC | 制造商:Cypress Semiconductor 功能描述: |
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