參數(shù)資料
型號(hào)： CY28326
廠商： Cypress Semiconductor Corp.
英文描述： FTG for VIA PT880 Serial Chipset
中文描述： FTG的威盛PT880系列芯片組
文件頁(yè)數(shù)： 2/23頁(yè)
文件大?。?/td> 288K
代理商： CY28326
CY28326
Document #: 38-07616 Rev. *A
Page 2 of 23
Pin Definition
Pin No.
1
Name
PWR
Type
I/O
Description
**FSA/REF0
VDDREF
Power-on Bi-directional Input/Output.
At power-up, FSA is the
input. when VTT_PWRGD transitions to a logic high, FSA state is
latched and this pin becomes REF0, buffered output copy of the
device’s XIN clock. Default Internal pull down.
Power-on Bi-directional Input/Output.
At power-up, FSB is the
input. when VTT_PWRGD transitions to a logic high, FSB state is
latched and this pin becomes REF1, buffered output copy of the
device’s XIN clock. Default Internal pull down.
3.3V Power supply for REF clock output.
Oscillator Buffer Input.
Connect to a crystal or to an external
clock.
Oscillator Buffer Input.
Connect to a crystal. Do not connect
when an external clock is applied at XIN.
Ground for REF clock outputs
Power-on Bi-directional Input/ Output.
At power up, FSC is the
input. When the VTT_PWRGD transitions to a logic high, FSC
state is latched and this pin becomes PCIF0. Default Internal pull
up.
Power-on Bi-directional Input/ Output.
At power up, FSD is the
input. When the VTT_PWRGD transitions to a logic high, FSD
state is latched and this pin becomes PCIF. Default Internal pull
up.
Power-on Bi-directional Input/ Output.
At power up,
MODE/PCIF2 is the input. When the power up, MODE state is
latched and then pin9 becomes PCIF2, PCI clock output for PCI
Device.Default pull-up, See
Table 2
3.3V power supply for PCI clock output.
Ground for PCI clock output.
PCI clock outputs.
Ratio0 Output/PCI5 Output.
At power up when RatioSel (pin 26)
strapping = “High” & MODE (pin 9) strapping=”High”, (PCI_STP#)
Ratio0/PCI5 becomes PCI5 clock output. At power up when
RatioSel (pin 26) strapping = “l(fā)ow” & MODE (pin 9) strapping
=”High”, (PCI_STP#)Ratio0/PCI5 becomes Ratio0 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio0/PCI5
becomes PCI_STP#, Default = “PCI5” see
Table 2
, Default
Internal pull up.
Ratio1 Output/PCI6 Output.
At power up when RatioSel(pin 26)
strapping = “High” & MODE(pin 9) strapping=”High”, (CPU_STP#)
Ratio1/PCI6 becomes PCI6 clock output. At power up when
RatioSel (pin 26) strapping = “l(fā)ow” & MODE(pin 9) strapping
=”High”, (PCI_STP#)Ratio1/PCI6 becomes Ratio1 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio1/PCI6
becomes CPU_STP#, Default = “PCI6” see
Table 2
, Default
Internal pull up.
48 MHz Clock Output.
Power-on Bi-directional Input/output.
At power up 24_48_SEL
is the input. When VTT_PWRGD is transited to logic high,
24_48_SEL state is latched and this pin becomes 24/48 MHz
output, Default 24_48_SEL= “0”, 48 MHz output.Default Internal
pull down.
Ground for 48 MHz clock output.
2
**FSB/REF1
VDDREF
I/O
3
4
VDDREF
XIN
I
I
VDDREF
5
XOUT
VDDREF
O
6
7
VSSREF
*FSC/PCIF0
PWR
I/O
VDDPCI
8
*FSD/PCIF1
VDDPCI
I/O
9
*MODE/
PCIF2
VDDPCI
I/O
10,17
11,18
VDDPCI
VSSPCI
PCI[0:4]
*(PCI_STP#)
Ratio0/PCI5
I
I
12,13,14,15,16
19
O
O
VDDPCI
20
*(CPU_STP#)
Ratio1/PCI6
VDDPCI
O
21
22
48 MHz
**24_48_SEL/
24_48 MHz
VDD48
VDD48
O
I/O
23
VSS48
I
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