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參數(shù)資料
| 型號： | CY28317PVXC-2T |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK FTG VIA PL/E133T 48SSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 248MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 48-SSOP |
| 包裝： | 帶卷 (TR) |
CY28317-2
..................... Document #: 38-07094 Rev. *B Page 15 of 20
Absolute Maximum Ratings[2]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only.
Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may affect reliability.
Parameter
Description
Rating
Unit
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
V
TSTG
Storage Temperature
–65 to +150
°C
TB
Ambient Temperature under Bias
–55 to +125
°C
TA
Operating Temperature
0 to +70
°C
ESDPROT
Input ESD Protection
2 (min.)
kV
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%
[3]
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD3
3.3V Supply Current
VDD = 3.465V,
FCPU = 133 MHz
250
mA
IDDPD3
3.3V Shut down Current
VDD = 3.465V
25
mA
Logic Inputs
VIL
Input Low Voltage
GND – 0.3
0.8
V
VIH
Input High Voltage
2.0
VDD + 0.3
V
IIL
Input Low Current[4]
–25
A
IIH
Input High Current[4]
10
A
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
50
mV
VOH
Output High Voltage
IOH = –1 mA
3.1
V
IOL
Output Low Current
PCI0:5
VOL = 1.5V
70
110
135
mA
REF0:1
VOL = 1.5V
50
70
100
mA
48 MHz
VOL = 1.5V
50
70
100
mA
24 MHz
VOL = 1.5V
50
70
100
mA
SDRAM
VOL = 1.5V
70
110
135
mA
IOH
Output High Current
PCI0:5
VOH = 1.5V
70
110
135
mA
REF0:1
VOH = 1.5V
50
70
100
mA
48 MHz
VOH = 1.5V
50
70
100
mA
24 MHz
VOH = 1.5V
50
70
100
mA
SDRAM
VOH = 1.5V
70
110
135
mA
Notes:
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. All clock outputs loaded with 6" 60
transmission lines with 20-pF capacitors.
4. CY28317-2 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
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