參數(shù)資料
型號(hào)： CY28317PVXC-2T
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 0K
描述： IC CLK FTG VIA PL/E133T 48SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:20
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 248MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-BSSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 48-SSOP
包裝： 帶卷 (TR)
CY28317-2
....................... Document #: 38-07094 Rev. *B Page 7 of 20
Bit 5
27
48MHz
1
(Active/Inactive)
Bit 4
26
24_48MHz
1
(Active/Inactive)
Bit 3
–
Reserved
1
Reserved
Bit 2
31, 30
SDRAM4:5
1
(Active/Inactive)
Bit 1
34, 33
SDRAM2:3
1
(Active/Inactive)
Bit 0
37, 36
SDRAM0:1
1
(Active/Inactive)
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
0
Reserved
Bit 0
–
Reserved
0
Reserved
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
CPU1
Stop Control
0
0 = CPU1 will be stopped when
CPU_STOP# is active
1 = CPU1 will NOT be stopped when
CPU_STOP# is active
Bit 3
–
CPU0
Stop Control
0
0 = CPU0 will be stopped when CPU_STOP# is active
1 = CPU0 will NOT be stopped when CPU_STOP# is
active
Bit 2
–
CPUT and CPUC
Stop
Control
0
0 = CPUT and CPUC will be stopped when
CPU_STOP# is active
1 = CPUT and CPUC will NOT be stopped when
CPU_STOP# is active
Bit 1
2
REF1
1
(Active/Inactive)
Bit 0
3
REF0
1
(Active/Inactive)
Byte 6: Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
PCI_Skew1
0
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
Bit 6
PCI_Skew0
0
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