參數(shù)資料
型號(hào): CXD3511Q
廠商: Sony Corporation
英文描述: Digital Signal Driver/Timing Generator
中文描述: 數(shù)字信號(hào)驅(qū)動(dòng)器/時(shí)序發(fā)生器
文件頁數(shù): 67/79頁
文件大?。?/td> 531K
代理商: CXD3511Q
67
CXD3511Q
(j)
R_OSD_DAT1 to 4[9:0], G_OSD_DAT1 to 4[9:0] and B_OSD_DAT1 to 4[9:0] (sub addresses: 014h
to 022h)
These set the OSD block decode data in 10 bits.
(k) GAM_SEL (sub address: 00Bh)
This selects the gamma block data path.
Setting value: 1 = Path passing through the RAM, 0 = Path not passing through the RAM
(l)
GAM_ON (sub address: 00Bh)
This sets the gamma block RAM operating mode.
Setting value: 1 = Normal operation, 0 = Standby mode
Note that in standby mode, data cannot be written to or read from the RAM. Also, previously set data is held
even when the RAM is set to standby mode.
(m) L_LIM_DAT[9:0] and H_LIM_DAT[9:0] (sub addresses: 026h and 027h)
This sets the limiter block limit value data in 10 bits.
Be sure to maintain the relationship L_LIM_DAT < H_LIM_DAT. Note that when both coefficients are set to
000h, limiter processing is not performed.
(n) MUTE2_ON (sub address: 028h)
This selects mute 2 block processing ON/OFF.
Setting value: 1 = Mute processing ON, 0 = OFF
(o) R_MUTE2[9:0], G_MUTE2[9:0] and B_MUTE2[9:0] (sub addresses: 023h to 025h)
These set the mute 2 block data in 10 bits.
(p) R1_POST_GAIN[7:0], R2_POST_GAIN[7:0], G1_POST_GAIN[7:0], G2_POST_GAIN[7:0],
B1_POST_GAIN[7:0] and B2_POST_GAIN[7:0] (sub addresses: 028h, 02Ah, 02Ch, 02Eh, 030h and
032h)
These set the post gain block arithmetic coefficients in 8 bits.
(q) R1_POST_BRT[6:0], R2_POST_BRT[6:0], G1_POST_BRT[6:0], G2_POST_BRT[6:0],
B1_POST_BRT[6:0] and B2_POST_BRT[6:0] (sub addresses: 029h, 02Bh, 02Dh, 02Fh, 031h and
033h)
These set the post bright block arithmetic coefficients in 7 bits with code.
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