參數(shù)資料
型號: CXD3021
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號處理器,具有內置數(shù)字伺服和DAC
文件頁數(shù): 148/161頁
文件大小: 1311K
代理商: CXD3021
– 148 –
CXD3021R
$3F (preset: $3F 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
ASFG FTQ LPAS SRO1 SRO0
AGHF
0
XT4D, XT2D:
MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the FSTIO pin clock. See the description of $3E for XT1D. And see "§ 4-12.
Clock System".
AGG4:
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is
as shown in the table below.
AGG4
0
1
AGGF
0
1
0
0
1
1
AGGT
0
1
0
1
0
1
FE input
conversion
1/32
×
V
DD
/2
1/16
×
V
DD
/2
TE input
conversion
1/16
×
V
DD
/2
1/8
×
V
DD
/2
DRR2 to DRR0
: Partially clears the Data RAM values (0 write).
The following values are cleared when 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note)
Set DRR1 and DRR0 on for 50μs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, the FCS servo filter
is forcibly set to gain normal status.
On when 1; default is 0
FTQ:
The focus search-up speed is set to the 1/4 value of that determined by FT1, FT0 and FTZ ($35).
On when 1; default is 0
See $37 for AGGF and AGGT.
The presets are AGG4 = 0,
AGGF = 1 and AGGT = 1.
: preset, —: don't care
: preset, —: don't care
XT1D
0
1
0
0
XT2D
0
1
0
XT4D
0
1
According to XTSL
1/1
1/2
1/4
Frequency division ratio
Sine wave amplitude
1/64
×
V
DD
/2
1/32
×
V
DD
/2
1/16
×
V
DD
/2
1/8
×
V
DD
/2
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