參數(shù)資料
型號： CXD3021
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù)： 111/161頁
文件大?。?/td> 1311K
代理商： CXD3021
– 111 –
CXD3021R
§ 5-2. Digital Servo Block Master Clock (MCK)
The FSTIO pin is the clock input/output pin for the servo block. At preset, the clock with 2/3 frequency of the
crystal is internally supplied to the servo block and the FSTIO pin serves as the monitor output pin for it. To
make this pin act as the input pin, set the command $8X command FSTIN to 1.
The master clock (MCK) is generated by dividing the frequency of the FSTIO pin. The frequency division ratio
is 1, 1/2 or 1/4.
Table 5-1 below assumes the preset status (where the clock with 2/3 frequency of the crystal is internally
supplied to the servo).
XT4D and XT2D are for the $3F command and XT1D is for the $3E command. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1/2
1/2
1
1/2
1/4
1/4
256Fs
128Fs
128Fs
512Fs
256Fs
128Fs
128Fs
XTLI
FSTO
XTSL
XT4D
XT2D
XT1D
Frequency division ratio
MCK
Fs = 44.1kHz,
: Don't care
Table 5-1.
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