參數(shù)資料
型號： CXD3021
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù)： 112/161頁
文件大小： 1311K
代理商： CXD3021
– 112 –
CXD3021R
§ 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.)
The CXD3021R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the
measurement results to control the servo effectively. This AVRG measurement and compensation is
necessary to initialize the CXD3021R, and is able to cancel the DC offset.
AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values
of 256 samples, and then loads these values into each AVRG register.
The AVRG measurement commands are VCLM, FLM, RFLM and TLM of $38.
Measurement is on when the respective command is set to 1.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received.
The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.)
Monitoring requires that the upper 8 bits of the command register are 38 (H).
XLAT
SENS
(= XAVEBSY)
Max. 1μs
AVRG measurement completed
2.9 to 5.8ms
Timing Chart 5-2.
<Measurement>
VC AVRG: The VC DC offset (VC AVRG) which is the center voltage for the system is measured and used to
compensate the FE, TE and SE signals.
FE AVRG: The FE DC offset (FE AVRG) is measured and used to compensate the FE and FZC signals.
TE AVRG: The TE DC offset (TE AVRG) is measured and used to compensate the TE and SE signals.
RF AVRG: The RF DC offset (RF AVRG) is measured and used to compensate the RFDC signal.
<Compensation>
RFLC:
(RF signal – RF AVRG) is input to the RF In register.
"00" is input when the RF signal is lower than RF AVRG.
(TE signal – VC AVRG) is input to the TRK In register.
(TE signal – TE AVRG) is input to the TRK In register.
(FE signal – VC AVRG) is input to the FCS In register.
(FE signal – FE AVRG) is input to the FCS In register.
(FE signal – FE AVRG) is input to the FZC register.
TLC0:
TLC1:
VCLC:
FLC1:
FLC0:
Two methods of canceling the DC offset are assumed for the CXD3021R. These methods are shown in Figs.
5-3a and 5-3b.
An example of AVRG measurement and compensation commands is shown below.
$38 08 00
(RF AVRG measurement)
$38 20 00
(FE AVRG measurement)
$38 00 10
(TE AVRG measurement)
$38 14 0A
(Compensation on [RFLC, FLC0, FLC1, TLC1], corresponds to Fig. 5-3a.)
See the description of $38 for these commands.
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