參數(shù)資料
型號(hào)： CXD3003R
廠商： Sony Corporation
元件分類： 數(shù)字信號(hào)處理
英文描述： CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述： CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù)： 95/137頁
文件大?。?/td> 1361K
代理商： CXD3003R
– 95 –
CXD3003R
§5-2. Digital Servo Block Master Clock (MCK)
The FSTI pin is the reference clock input pin. The internal master clock (MCK) is generated by dividing the
frequency of the signal input to FSTI. The frequency division ratio is 1, 1/2 or 1/4.
Table 5-1 below assumes that the crystal clock generated from the digital signal processor block which is 2/3
frequency-divided of XTLI is input to the FSTI pin by externally connecting the FSTI pin and the FSTO pin.
The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with
D1 of $3E. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode
1
2
3
4
5
6
7
384Fs
384Fs
384Fs
768Fs
768Fs
768Fs
768Fs
256Fs
256Fs
256Fs
512Fs
512Fs
512Fs
512Fs
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1/2
1/2
1
1/2
1/4
1/4
256Fs
128Fs
128Fs
512Fs
256Fs
128Fs
128Fs
XTLI
FSTO (FSTI)
XTSL
XT4D
XT2D
XT1D
Frequency division ratio
MCK
Fs = 44.1kHz,
: Don’t care
Table 5-1.
§5-3. AVRG (Average) Measurement and Compensation
The CXD3003R has a circuit that measures AVRG of RFDC, VC, FE and TE and a circuit that compensates
these signals to control the servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD3003R, and is able to cancel the
offset.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then
loads each value into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is
received.
During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.)
XLAT
SENS
(= XAVEBSY)
Max. 1μs
AVRG measurement completed
2.9 to 5.8ms
Timing Chart 5-2.
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