參數(shù)資料
型號(hào): CXD3003R
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號(hào)處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù): 42/137頁
文件大小: 1361K
代理商: CXD3003R
– 42 –
CXD3003R
Command
Data 3
Function
specification
DAC
EMPH
DAC
ATT
0
0
D15
D14
D13
D12
These command bits control the DAC.
Note)
For normal stereo, channel 1 is the left channel and channel 2 is the right channel.
Command bit
DAC EMPH = 1
DAC EMPH = 0
Applies digital de-emphasis. The emphasis constants are
τ
1 = 50μs and
τ
2 = 15μs
when Fs = 44.1kHz.
Turns digital de-emphasis off.
Processing
Command bit
DAC ATT = 1
DAC ATT = 0
Identical digital attenuation control is used for both channels 1 and 2. When common
attenuation data is specified, the attenuation values for channel 1 are used.
Independent digital attenuation control is used for both channels 1 and 2.
Processing
I/O sync circuit
Related pins: LRCK and XWO, Related command: XWOC
During normal operation, the I/O sync circuit automatically synchronizes with the input LRCK, and its operation
proceeds in phase with the serial input data. However, there is a chance that synchronization will not be
performed if there is a great deal of jitter in LRCK, or if the power has just been turned on, etc. In this case,
forced synchronization is possible by setting the XWO pin or command XWOC low (0) for 2/Fs or more. Forced
synchronization must also be performed when switching the clock system such as when switching from CLV
mode to CAV mode and vice versa, or when switching the operating frequency, etc. The forced
synchronization operation is performed at the second rising edge of LRCK after the XWO pin is set low or the
XWOC command 19 set to 0.
This is used to perform resynchronization to DAC.
This command has the function equal to the external pin XWO's.
Set to high or 1 for the external pin or unused side of the command register.
Command bit
External pin
XWOC
XWO
Processing
DAC sync window is open.
DAC sync window is not open.
0
0
1
1
L
H
L
H
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