參數(shù)資料
型號: CXD3000R
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù): 71/129頁
文件大?。?/td> 1264K
代理商: CXD3000R
– 71 –
CXD3000R
Timing Chart 4-3
Normal-speed PB
400 to 500ns
RFCK
MNT3
MNT1
MNT0
t = Dependent on error
condition
C1 correction
C2 correction
Strobe
Strobe
MNT2
§4-4. DA Interface
The CXD3000R has two DA interface modes.
a) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
b) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
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