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參數(shù)資料
| 型號(hào)： | CXD3000R |
| 廠商： | Sony Corporation |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁(yè)數(shù)： | 15/129頁(yè) |
| 文件大小： | 1264K |
| 代理商： | CXD3000R |
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CXD3000R
Contents
[1] CPU Interface
§1-1.
§1-2.
§1-3.
§1-4.
CPU Interface Timing ........................................................................................................................ 16
CPU Interface Command Table ........................................................................................................ 16
CPU Command Presets .................................................................................................................... 26
Description of SENS Signals ............................................................................................................. 31
[2] Subcode Interface
§2-1.
P to W Subcode Readout .................................................................................................................. 60
§2-2.
80-bit Sub Q Readout ........................................................................................................................ 60
[3] Description of Modes
§3-1.
CLV-N Mode ...................................................................................................................................... 66
§3-2.
CLV-W Mode ..................................................................................................................................... 66
§3-3.
CAV-W Mode ..................................................................................................................................... 66
[4] Description of Other Functions
§4-1.
Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 68
§4-2.
Frame Sync Protection ...................................................................................................................... 70
§4-3.
Error Correction ................................................................................................................................. 70
§4-4.
DA Interface ....................................................................................................................................... 71
§4-5.
Digital Out .......................................................................................................................................... 74
§4-6.
Servo Auto Sequence ....................................................................................................................... 75
§4-7.
Digital CLV ......................................................................................................................................... 83
§4-8.
Playback Speed ................................................................................................................................ 84
§4-9.
DAC Block Playback Speed .............................................................................................................. 85
§4-10. DAC Block Input Timing .................................................................................................................... 85
§4-11. Asymmetry Compensation ................................................................................................................ 86
§4-12. CXD3000 Clock System .................................................................................................................... 87
[5] Description of Servo Signal Processing System Functions and Commands
§5-1.
General Description of the Servo Signal Processing System ............................................................ 88
§5-2.
Digital Servo Block Master Clock (MCK) ........................................................................................... 89
§5-3.
AVRG Measurement and Compensation .......................................................................................... 89
§5-4.
E:F Balance Adjustment Function ..................................................................................................... 91
§5-5.
FCS Bias Adjustment Function .......................................................................................................... 91
§5-6.
AGCNTL Function ............................................................................................................................. 93
§5-7.
FCS Servo and FCS Search ............................................................................................................. 95
§5-8.
TRK and SLD Servo Control ............................................................................................................. 96
§5-9.
MIRR and DFCT Signal Generation .................................................................................................. 97
§5-10. DFCT Countermeasure Circuit .......................................................................................................... 98
§5-11. Anti-Shock Circuit .............................................................................................................................. 98
§5-12. Brake Circuit ...................................................................................................................................... 99
§5-13. COUT Signal ................................................................................................................................... 100
§5-14. Serial Readout Circuit ...................................................................................................................... 100
§5-15. Writing to the Coefficient RAM ........................................................................................................ 101
§5-16. PWM Output .................................................................................................................................... 101
§5-17. DIRC Input Pin ................................................................................................................................. 103
§5-18. Servo Status Changes Produced by the LOCK Signal ................................................................... 104
§5-19. Description of Commands and Data Sets ....................................................................................... 104
§5-20. List of Servo Filter Coefficients ........................................................................................................ 117
§5-21. Filter Composition ............................................................................................................................ 119
§5-22. TRACKING and FOCUS Frequency Response .............................................................................. 126
[6] Application Circuit
.................................................................................................................................. 127
Explanation of abbreviations
AVRG:
AGCNTL: Auto gain control
FCS:
Focus
TRK:
Tracking
SLD:
Sled
DFCT:
Defect
Average
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相關(guān)代理商/技術(shù)參數(shù) |
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| CXD3003 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
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| CXD3008Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo |
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