參數(shù)資料
型號： CXD2721Q-1
廠商： Sony Corporation
元件分類： 數(shù)字信號處理
英文描述： Single-Chip Digital Signal Processor for Karaoke
中文描述： 單芯片數(shù)字信號處理器的卡拉OK
文件頁數(shù)： 44/70頁
文件大?。?/td> 941K
代理商： CXD2721Q-1
– 44 –
CXD2721Q-1
7-3-4. Surround
[Relevant coefficients] kLri (address = 15H), KRri (address = 16H), HDmp0 (address = 38H),
HDmp1 (address = 39H), KLe0 (address = 3AH), KLe1 (address = 3BH),
KRe0 (address = 3CH), KRe1 (address = 3DH), Kfb (address = 3EH),
KLtp0 (address = 3FH), KLtp1 (address = 40H), KLtp2 (address = 41H),
KLtp3 (address = 42H), KLtp4 (address = 43H), KLtp5 (address = 44H),
KLtp6 (address = 45H), KLtp7 (address = 46H), bL0 (address = 47H),
bL1 (address = 48H), KRtp0 (address = 4BH), KRtp1 (address = 4CH),
KRtp2 (address = 4DH), KRtp3 (address = 4EH), KRtp4 (address = 4FH),
KRtp5 (address = 50H), KRtp6 (address = 51H), KRtp7 (address = 52H),
bR0 (address = 53H), bR1 (address = 54H), TdiER (address = 55H),
LER0 (address = 56H), LER1 (address = 57H), RER0 (address = 58H),
RER1 (address = 59H), TdoES (address = 5AH), TdiSR (address = 5BH),
Ltp0 (address = 5CH), Ltp1 (address = 5DH), Ltp2 (address = 5EH),
Ltp3 (address = 5FH), Ltp4 (address = 60H), Ltp5 (address = 61H),
Ltp6 (address = 62H), Ltp7 (address = 63H), Lap0i (address = 64H),
Lap0o (address = 65H), Lap1i (address = 66H), Lap1o (address = 67H),
Rtp0 (address = 68H), Rtp1 (address = 69H), Rtp2 (address = 6AH),
Rtp3 (address = 6BH), Rtp4 (address = 6CH), Rtp5 (address = 6DH),
Rtp6 (address = 6EH), Rtp7 (address = 6FH), Rap0i (address = 70H),
Rap0o (address = 71H), Rap1i (address = 72H), Rap1o (address = 73H),
TdoSR (address = 74H)
Delay amount setting
The built-in delay RAM capacity which can be used in music mode is 128K bits (approximately 185ms). The
surround block has a number of delay lines for initial reverberation sound and higher-order reverberation
sound, and the delay RAM can be assigned freely to these delay lines.
However, the following restrictions apply.
0000H
≤
TdoES
≤
FFD0H
TdoES
≤
TdiSR
≤
FFD0H
TdiSR + TdoSR
≤
FFD0H
TdiSR + Lap0i
≤
FFD8H (Lap0i
≥
TdoSR + 0008H)
TdiSR + Lap0o
≤
FFE0H (Lap0o
≥
0008H)
TdiSR + Lap1i
≤
FFE0H (Lap1i
≥
Lap0o)
TdiSR + Lap1o
≤
FFE8H (Lap1o
≥
0008H)
TdiSR + Rap0i
≤
FFE8H (Rap0i
≥
Lap1o)
TdiSR + Rap0o
≤
FFF0H (Rap0o
≥
0008H)
TdiSR + Rap1i
≤
FFF0H (Rap1i
≥
Rap0o)
TdiSR + Rap1o
≤
FFF8H (Rap1o
≥
0008H)
→
Determines the initial reverberation sound delay amount
→
Determines the higher-order reverberation sound delay amount
(LER0, LER1, RER0, RER1)
≤
TdoER
(Ltp
, Rtp
)
≤
TdoSR
As shown above, the delay amount can be set to "0" for all delay lines other than the all-pass filter for through
operation.
Fig. 7-3-4 shows the setting example where the delay RAM is used to the fullest extent.
Also, the relationships between the delay amount and coefficients are shown in Table 7-3-4.
相關(guān)PDF資料
PDF描述
CXD2724AQ-3 Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞邏輯譯碼器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CXD2724AQ-1 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
CXD2724AQ-3 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
CXD2728Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder
CXD2917 制造商:SONY 制造商全稱:Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION
CXD2917Q 制造商:SONY 制造商全稱:Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION
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