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參數(shù)資料
| 型號(hào)： | CXD2721Q-1 |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Single-Chip Digital Signal Processor for Karaoke |
| 中文描述： | 單芯片數(shù)字信號(hào)處理器的卡拉OK |
| 文件頁(yè)數(shù)： | 25/70頁(yè) |
| 文件大?。?/td> | 941K |
| 代理商： | CXD2721Q-1 |
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CXD2721Q-1
(4)-2. Read
First, address and mode section data are transferred synchronized to SCK, and XLAT rises together with this.
The procedure until this point is the same as for write, so the description is omitted here.
Read differs from write in that after XLAT rises, REDY falls within 3
t
+ 50ns (
t
LBD
), and the microcomputer is
informed of SV cycle waiting.
At this time, the TRDT pin changes from high-impedance status to active status (
t
LDN
≤
3
t
+ 80ns) simultaneously
with the fall of REDY. When the read data is ready, the REDY pin changes from Low to High. When the data
read out from the TRDT pin is made TR, and SCK falls (
t
RSDP
≥
20ns) when the REDY pin goes High, the first
TR data is established within 2
t
+ 70ns (
t
SDD
). The microcomputer reads this data at the SCK rise. The TR
data is read in order from the LSB with 16 bits for the coefficient RAM and 24 bits for the setup register by
adding SCK. When all the corresponding data is read, read is completed.
Next, the method for restarting transfer after read is completed is described.
As in Case 1, there is a method for sending address and mode section data consecutively after reading all of
the 16- or 24-bit data. 2
t
+ 40ns or more should be left between the SCK rise for the final data read and the
next SCK rise (
t
SS
), and this is established by the conditions
t
SWL
≥
1
t
+ 20ns and
t
SWH
≥
1
t
+ 20ns. Further, at
this read REDY changes from High to Low, but it is prohibited for the XLAT for the next transfer to fall before
this. If REDY = Low has been established, XLAT can fall (
t
LDR
≥
20ns).
Also, while 16- or 24-bit data is being read from the TRDT pin, address and mode section data writing to the
RVDT pin for the next transfer can be started.
In Case 3, the final section of read data and the final data in the mode section overlap, and this allows shifting
to the next transfer processing in the shortest possible time after data read.
It is also possible to have data read and address and mode section write overlap partially, as shown by Case
2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD2724AQ-3 | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞邏輯譯碼器) |
| CXD2728Q | Single-Chip Dolby Pro Logic Surround Decoder(單片杜比環(huán)繞Pro邏輯解碼器) |
| CXD2930BR | GPS LSI With Built-In 32-Bit RISC CPU(全球定位系統(tǒng)（GPS）大規(guī)模集成電路(LSI)(內(nèi)置32位RISC中央處理器)) |
| CXD2931R | 1 Chip GPS LSI(單片全球定位系統(tǒng)（GPS）大規(guī)模集成電路LSI) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2724AQ-1 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2724AQ-3 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2728Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Single-Chip Dolby Pro Logic Surround Decoder |
| CXD2917 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION |
| CXD2917Q | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:DIGITAL AUDIO DATA MODULATION AND TRANSMISSION |
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