參數(shù)資料
型號: CXD2548R
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù): 84/113頁
文件大?。?/td> 1286K
代理商: CXD2548R
– 84 –
CXD2548R
§4-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz and loaded. The MIRR and
DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of these envelope waveforms.
The MIRR signal is generated by comparing this MIRR comparator level with the waveform generated by
subtracting the bottom hold value from the peak hold value. (See Fig. 4-6.)
RF
Peak Hold
Bottom Hold
Peak Hold
–Bottom Hold
MIRR
MIRR Comp
(Mirror comparator level)
H
L
RF
Peak Hold1
Peak Hold2
Peak Hold2
–Peak Hold1
DFCT
(Defect
comparator level)
H
L
SDF
Fig. 4-6.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 4-7.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
Fig. 4-7.
相關PDF資料
PDF描述
CXD2552 1 BIT D/A CONVERTER
CXD2552Q 1 BIT D/A CONVERTER
CXD2597Q CD Digital Signal Processor with Built-in Digital Servo and DAC
CXD2720Q-2 CAP 10UF 50V 20% TANT SMD-7343-43 TR-13 GOLD
CXD2724AQ-1 Single-Chip Dolby Pro Logic Surround Decoder
相關代理商/技術參數(shù)
參數(shù)描述
CXD2550P 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Filter for CD
CXD2551M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter
CXD2551M/P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter
CXD2551P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter
CXD2552 制造商:SONY 制造商全稱:Sony Corporation 功能描述:1 BIT D/A CONVERTER