參數(shù)資料
型號(hào): CXD2548R
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號(hào)處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁(yè)數(shù): 42/113頁(yè)
文件大小: 1286K
代理商: CXD2548R
– 42 –
CXD2548R
$DX commands
Command bit
Description
DCLV PWM MD = 1
DCLV PWM MD = 0
Digital CLV PWM mode specified. Both MDS and MDP are used.
CLV-W and CAV-W modes can not be used.
Digital CLV PWM mode specified. Ternary MDP values are output.
CLV-W and CAV-W modes can be used.
Command bit
Description
TB = 0
TB = 1
TP = 0
TP = 1
Bottom hold at a cycle of RFCK/32 in CLVS mode.
Bottom hold at a cycle of RFCK/16 in CLVS mode.
Peak hold at a cycle of RFCK/4 in CLVS mode.
Peak hold at a cycle of RFCK/2 in CLVS mode.
Command
D23
DCLV
PWM MD
TB
TP
Gain
CLVS
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
Data 1
Data 2
CLV CTRL
Data 3
See "$CX Commands".
Command bit
Description
VP0 to 7 = F0 (H)
:
VP0 to 7 = E0 (H)
Playback at half (normal) speed
to
Playback at normal (double) speed
The rotational velocity R of the spindle can be
expressed with the following equation.
R =
32
256 – n
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
Notes)
1) Values in parentheses are for when DSPB is 1.
2) Values when the crystal is 16.9344MHz and XTSL is low or when the crystal is 33.8688MHz and XTSL is
high.
3) The VP0 to 7 setting values are valid in CAV-W mode.
2
R
1.5
1
0.5
F0
E0
VP0 to 7 setting value [HEX]
DSPB = 1
DSPB = 0
Fig. 2-1.
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