參數(shù)資料
型號(hào): CXD2548R
廠商: Sony Corporation
元件分類: 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號(hào)處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁數(shù): 33/113頁
文件大?。?/td> 1286K
代理商: CXD2548R
– 33 –
CXD2548R
Command bit
VCOSEL1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to normal speed, and the output is 1/2
frequency-divided.
Multiplier PLL VCO1 is set to normal speed, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to normal speed, and the output is 1/8
frequency-divided.
Multiplier PLL VCO1 is set to high speed
1
, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to high speed
1
, and the output is 1/2
frequency-divided.
Multiplier PLL VCO1 is set to high speed
1
, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to high speed
1
, and the output is 1/8
frequency-divided.
KSL3
KSL2
Processing
1
Approximately twice the normal speed
Command bit
VCOSEL2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1
frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2
frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8
frequency-divided.
Wide-band PLL VCO2 is set to high speed
2
, and the output is 1/1
frequency-divided.
Wide-band PLL VCO2 is set to high speed
2
, and the output is 1/2
frequency-divided.
Wide-band PLL VCO2 is set to high speed
2
, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to high speed
2
, and the output is 1/8
frequency-divided.
KSL1
KSL0
Processing
2
Approximately twice the normal speed
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