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參數(shù)資料
| 型號(hào)： | CX72302-11 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28 |
| 封裝： | EXPOSED PAD, TSSOP-28 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 162K |
| 代理商： | CX72302-11 |
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101216G Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 22, 2004
15
Table 5. CX72302 Signal Descriptions
Pin #
Pin Name
Type
Description
1
Clock
Digital input
Clock signal pin. When CS is low, the register address and data are shifted in address bits first on the
Data pin on the rising edge of Clock.
2
Mod_in
Digital input
Alternate serial modulation data input pin. Address bits are followed by data bits.
3
Mux_out
Digital output
Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main
or auxiliary divided VCO frequency, serial data out, or testability signals. This pin can be three-stated from
the general synthesizer registers.
4
VSUBdigital
–
Substrate isolation. Connect to ground.
5
GNDecl/cml (Note 1)
Power and ground
Emitter Coupled Logic (ECL)/Current Mode Logic (CML) ground.
6
VCCcml_main
(Note 1)
Power and ground
ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump.
7
Fvco_main
Input
Main VCO differential input.
8
Fvco_main
Input
Main VCO complimentary differential input.
9
LD/PSmain
Analog output
Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This
pin is configured from the general synthesizer registers.
10
VCCcp_main
(Note 1)
Power and ground
Main charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and
charge pump.
11
CPout_main
Analog output
Main charge pump output. The gain of the main charge pump phase detector can be controlled from the
general synthesizer registers.
12
GNDcp_main
(Note 1)
Power and ground
Main charge pump ground.
13
Xtalacgnd/OSC
Ground/input
Reference crystal AC ground or external oscillator differential input.
14
Xtalin/OSC
Input
Reference crystal input or external oscillator differential input.
15
Xtalout/NC
Input
Reference crystal output or no connect.
16
VCCxtal
Power and ground
Crystal oscillator ECL/CML 3 V.
17
GNDxtal
Power and ground
Crystal oscillator ground.
18
LD/PSaux
Analog output
Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open
collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO.
This pin is configured from the general synthesizer registers.
19
VCCcp_aux (Note 1)
Power and ground
Auxiliary charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and
charge pump.
20
CPout_aux
Analog output
Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector can be controlled
from the general synthesizer registers.
21
GNDcp_aux (Note 1)
Power and ground
Auxiliary charge pump ground.
22
Fvco_aux
Input
Auxiliary VCO complimentary differential input.
23
Fvco_aux
Input
Auxiliary VCO differential input.
24
VCCcml_aux
(Note 1)
Power and ground
ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump.
25
GNDdigital (Note 1)
Power and ground
Digital ground.
26
VCCdigital (Note 1)
Power and ground
Digital 3 V.
27
Data
Digital input
Serial address and data input pin. Address bits are followed by data bits.
28
CS
Digital input
Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock.
When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges
are ignored.
Note 1: Associated pairs of power and ground pins must be decoupled using 0.1
F capacitors.
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