參數(shù)資料
型號(hào): CX72302-11
廠商: SKYWORKS SOLUTIONS INC
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28
封裝: EXPOSED PAD, TSSOP-28
文件頁數(shù): 20/20頁
文件大?。?/td> 162K
代理商: CX72302-11
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
101216G Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 22, 2004
9
Table 1. CX72302 Register Map
Address (Hex)
Register (Note 1)
Length (Bits)
Address (Bits)
0
Main Divider Register
12
4
1
Main Dividend MSB Register
12
4
2
Main Dividend LSB Register
12
4
3
Auxiliary Divider Register
12
4
Auxiliary Dividend Register
12
4
5
Reference Frequency Dividers Register
12
4
6
Control Register—phase detector/charge pumps
12
4
7
Control Register—power down/multiplexer output select
12
4
8
Modulation Control Register
12
4
9
Modulation Data Register
Modulation Data Register (Note 2) — direct input
12
2
≤ length ≤ 12 bits
4
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
A3
A2 A1
A0 11
10
9
8
7
6
5
4
3
2
1
0
00
X
X MSB
LSB
Main Synthesizer Divider Index
C1417
Figure 6. Main Divider Register (Write Only)
Synthesizer Registers
Main Synthesizer Registers. The Main Divider Register contains
the integer portion closest to the desired fractional-N (or the
integer-N) value minus 32 for the main synthesizer. This register,
in conjunction with the Main Dividend Registers (which control the
fraction offset from –0.5 to +0.5), allows selection of a precise
frequency.
NOTE: The fixed divide-by-four divider upstream from the
programmable main divider must be taken into
consideration to determine the value to be programmed
in this register. For more information, refer to the
Synthesizer Register Programming section in this
document.
As shown in Figure 6, the value to be loaded is:
Main Synthesizer Divider Index = 9-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB and LSB Registers control the fraction
part of the desired fractional-N value and allow an offset of –0.5
to + 0.5 to the main integer selected through the Main Divider
Register. As shown in Figures 7 and 8, the values to be loaded
are:
Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of
the 18-bit dividend for the main synthesizer.
The Main Dividend MSB and LSB Register values are 2's
complement format.
NOTE: When in 10-bit mode, the Main Synthesizer Dividend
(LSBs) is not required.
For information on programming and loading order for these
registers, see the Operation section in this document.
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