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參數(shù)資料
| 型號： | CX72302-11 |
| 廠商： | SKYWORKS SOLUTIONS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 6100 MHz, PDSO28 |
| 封裝： | EXPOSED PAD, TSSOP-28 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 162K |
| 代理商： | CX72302-11 |
DATA SHEET CX72302
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
12
July 22, 2004 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 101216G
The Control Register allows control of the gain for both phase
detectors and configuration of the LD/PSmain and LD/PSaux pins
for frequency power steering or lock detection. As shown in
Figure 12, the values to be loaded are:
Main Phase Detector Gain = 5-bit value for programmable main
phase detector gain. Range is from 0 to 31 decimal for 31.25 to
1000
A/2π radian, respectively.
Main Power Steering Enable = 1-bit value to enable the
frequency power steering circuitry of the main phase detector.
When this bit is a 0, the LD/PSmain pin is configured to be a
lock detect, active-low, open collector pin. When this bit is a 1,
the LD/PSmain pin is configured to be a frequency power
steering pin and can be used to bypass the external main loop
filter to provide faster frequency acquisition.
Auxiliary Phase Detector Gain = 5-bit value for programmable
auxiliary phase detector gain. Range is from 0 to 31 decimal for
31.25 to 1000
A/2π radian, respectively.
Auxiliary Power Steering Enable = 1-bit value to enable the
frequency power steering circuitry of the auxiliary phase
detector. When this bit is a 0, the LD/PSaux pin is configured to
be a lock detect, active-low, open collector pin. When this bit is
a 1, the LD/PSaux pin is configured to be a frequency power
steering pin and may be used to bypass the external auxiliary
loop filter to provide faster frequency acquisition.
The Power Down and Multiplexer Output Register allows control
of the power-down modes, internal multiplexer output, and main
Σ synthesizer fractionality. As shown in Figure 13, the values to
be loaded are:
Full Power Down = 1-bit value that powers down the CX72302
except for the reference oscillator and the serial interface. When
this bit is 0, the CX72302 is powered up. When this bit is 1, the
CX72302 is in full power-down mode excluding the Mux_out
pin.
Main Synthesizer Power Down = 1-bit value that powers down
the main synthesizer. When this bit is 0, the main synthesizer is
powered up. When this bit is 1, the main synthesizer is in
power-down mode.
A3
A2 A1
A0 11
10
9
8
7
6
5
4
3
2
1
0
01
10
Main Phase Detector Gain
Main Power Steering/Lock Detect Enable
Auxiliary Phase Detector Gain
Auxiliary Power Steering/Lock Detect Enable
C1423
Figure 12. Control Register (Write Only)
A3
A2 A1
A0 11
10
9
8
7
6
5
4
3
2
1
0
01
11
X
MSB
LSB
Full Power Down
Main Synthesizer Power Down
Main Synthesizer Mode
Main Synthesizer
Σ Fractionality
Auxiliary Synthesizer Power Down
Auxiliary Synthesizer Mode
Multiplexer Output Selection
Mux_out Pin Three-State Enable
C1424
Figure 13. Power Down and Multiplexer Output Register (Write Only)
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