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參數(shù)資料
| 型號： | CS8414-CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 96 KHZ DIGITAL AUDIO RECEIVER |
| 中文描述： | 96 kHz的數(shù)字音頻接收器 |
| 文件頁數(shù)： | 37/38頁 |
| 文件大?。?/td> | 646K |
| 代理商： | CS8414-CS |
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CS8413 CS8414
8
DS240F1
are extracted at times when intersymbol interfer-
ence is at a minimum. This provides a sample fre-
quency clock that is as spectrally pure as the digital
audio source clock for moderate length transmis-
sion lines. For long transmission lines, the CS8413
can be programmed to generate FSYNC from
MCK instead of from the incoming data.
CS8413 DESCRIPTION
The CS8413 is more flexible than the CS8414 but
requires a microcontroller or DSP to load internal
registers. The CS8414 does not have internal regis-
ters so it may be used in a stand-alone mode where
a microprocessor or DSP is not available.
The CS8413 accepts data from a transmission line
coded according to the digital audio interface stan-
dards. The I.C. recovers clocks and data, and sepa-
rates the audio data from control information. The
audio data is output through a configurable serial
port and the control information is stored in internal
dual-port RAM. Extensive error reporting is avail-
able via internal registers with the option of repeat-
ing the last sample when an error occurs. A block
diagram of the CS8413 is shown in Figure 4
Parallel Port
The parallel port accesses two status registers, two
interrupt enable registers, two control registers, and
28 bytes of dual-port buffer memory. The status
registers and interrupt enable registers occupy the
same address space. A bit in control register 1 se-
lects the two registers, either status or interrupt en-
able, that occupy addresses 0 and 1 in the memory
map. The address bus and the RD/WR line should
be valid when CS goes low. If RD/WR is low, the
value on the data bus will be written into the buffer
memory at the specified address. If RD/WR is high,
the value in the buffer memory, at the specified ad-
dress, is placed on the data bus. Detailed timing for
the parallel port can be found in the Switching
Characteristics - Parallel Port table.
The memory space on the CS8413 is allocated as
shown in Figure 5. There are three defined buffer
modes selectable by two bits in control register 1.
Further information on the buffer modes can be
found in the Control Registers section.
10
2
10
3
10
4
10
5
10
6
-30
-25
-20
-15
-10
-5
0
5
Jitter Frequency (Hz)
Jit
ter
At
tenu
at
ion
(d
B
)
Figure 3. Typical Jitter Attenuation Characteristics
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS8414-CSR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述: |
| CS8414-CSZ | 功能描述:音頻 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| CS8414-CSZ/A | 制造商:Cirrus Logic 功能描述: |
| CS8414-CSZR | 功能描述:音頻 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| CS8415A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:96 kHz DIGITAL AUDIO INTERFACE RECEIVER |
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