參數(shù)資料
型號(hào)： CS8414-CS
廠商： Electronic Theatre Controls, Inc.
英文描述： 96 KHZ DIGITAL AUDIO RECEIVER
中文描述： 96 kHz的數(shù)字音頻接收器
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 646K
代理商： CS8414-CS
CS8413 CS8414
DS240F1
19
The two most significant bits in SR1 change defini-
tion for buffer mode 2. These two bits, when set, in-
dicate CRC errors for their respective channels. A
CRC error occurs when the internal calculated
CRC for channel status bytes 0 through 22 does not
match channel status byte 23. CCHG, bit 5 in SR1,
is set when any bit in the first four channel status
bytes of either channel changes from one block to
the next. Since channel status doesn’t change very
often, this bit may be monitored rather than check-
ing all the bits in the first four bytes. These bits are
illustrated in Figure 6.
Buffer Updates and Interrupt Timing
As mentioned previously in the buffer mode sec-
tions, conflicts between externally reading the
buffer RAM and the CS8413 internally writing to it
may be averted by using the flag levels to avoid the
section currently being addressed by the part. How-
ever, if the interrupt line, along with the flags, is
utilized, the actual byte that was just updated can be
determined. In this way, the entire buffer can be
read
without
concern
for
internal
updates.
Figure 15 shows the detailed timing for the inter-
rupt line, flags, and the RAM write line. SCK is 64
times the incoming sample frequency, and is the
same SCK output in master mode. The FSYNC
shown is valid for all master modes except the I2S
compatible mode. The interrupt pulse is shown to
be 4 SCK periods wide and goes low 5 SCK peri-
ods after the RAM is written. Using the above in-
formation, the entire data buffer may be read
starting with the next byte to be updated by the in-
ternal pointer.
ERF Pin Timing
ERF signals that an error occurred while receiving
the audio sample that is currently being read from
the serial port. ERF changes with the active edge of
FSYNC and is high during the erroneous sample.
ERF is affected by the error conditions reported in
SR2: LOCK, CODE, PARITY, and V. Any of
these conditions may be masked off using the cor-
responding bits in IER2. The ERF pin will go high
for each error that occurs. The ERF bit in SR1 is
different from the ERF pin in that it only causes an
interrupt the first time an error occurs until SR1 is
read. More information on the ERF pin and bit is
FSYNC
(FLAG0,1)
(FLAG2)
SCK
Left 191
Right 191
Left 0
INT
IWRITE
INT
FSF1,0
MSTR
SCED
= 1
= 1 0
Figure 15. RAM/Buffer - Write and Interrupt Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS8414-CSR 制造商:Rochester Electronics LLC 功能描述: 制造商:Cirrus Logic 功能描述:
CS8414-CSZ 功能描述:音頻 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
CS8414-CSZ/A 制造商:Cirrus Logic 功能描述:
CS8414-CSZR 功能描述:音頻 DSP IC 96 kHz Digital Audio Receivers RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube
CS8415A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:96 kHz DIGITAL AUDIO INTERFACE RECEIVER
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