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參數(shù)資料
| 型號： | CS5530-ISZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 1CH W/LNA 20SSOP |
| 標準包裝： | 66 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1158-ND - BOARD EVAL FOR CS5530 |
| 其它名稱： | 598-1283-5 |
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CS5530
DS742F3
23
For maximum accuracy, calibrations should be per-
formed for both offset and gain.
When the device is used without calibration, the
uncalibrated gain accuracy is about ±1 percent.
Note that the gain from the offset register to the
output is 1.83007966 decimal, not 1. If a user wants
to adjust the calibration coefficients externally,
they will need to divide the information to be writ-
ten to the offset register by the scale factor of
1.83007966. (This discussion assumes that the gain
register is 1.000...000 decimal. The offset register
is also multiplied by the gain register before being
applied to the output conversion words).
2.4.7 Limitations in Calibration Range
System calibration can be limited by signal head-
room in the analog signal path inside the chip as
discussed under the Analog Input section of this
data sheet. For gain calibration, the full-scale input
signal can be reduced to 3% of the nominal full-
scale value. At this point, the gain register is ap-
proximately equal to 33.33 (decimal). While the
gain register can hold numbers all the way up to
64 - 2-24, gain register settings above a decimal
value of 40 should not be used. With the convert-
er’s intrinsic gain error, this minimum full-scale in-
put signal may be higher or lower. In defining the
minimum full-scale Calibration Range (FSCR) un-
der Analog Characteristics, margin is retained to
accommodate the intrinsic gain error. Inversely, the
input full-scale signal can be increased to a point in
which the modulator reaches its 1’s density limit of
86 percent, which under nominal conditions occurs
when the full-scale input signal is 1.1 times the
nominal full-scale value. With the chip’s intrinsic
gain error, this maximum full-scale input signal
maybe higher or lower. In defining the maximum
FSCR, margin is again incorporated to accommo-
date the intrinsic gain error.
2.5 Performing Conversions
The CS5530 offers two distinctly different conver-
sion modes. The paragraphs that follow detail the
differences in the conversion modes.
2.5.1 Single Conversion Mode
When the user transmits the perform single conver-
sion command, a single, fully settled conversion is
performed using the word rate and polarity selec-
tions set in the configuration register. Once the
command byte is transmitted, the serial port enters
data mode where it waits until the conversion is
complete. When the conversion data is available,
SDO falls to logic 0 to act as a flag to indicate that
the data is available. Forty SCLKs are then needed
to read the conversion data word. The first 8
SCLKs are used to clear the SDO flag. During the
first 8 SCLKs, SDI must be logic 0. The last 32
SCLKs are needed to read the conversion result.
Note that the user is forced to read the conversion
in single conversion mode as the serial port will re-
main in data mode until SCLK transitions 40 times.
After reading the data, the serial port returns to the
command mode, where it waits for a new command
to be issued. The single conversion mode will take
longer than conversions performed in the continu-
ous conversion mode. The number of clock cycles
a single conversion takes for each Output Word
(FRS = 0) or ± 10 (FRS = 1) clock ambiguity is due
to internal synchronization between the SCLK in-
put and the oscillator.
Note:
In the single conversion mode, more than one
conversion is actually performed, but only the
final, fully settled result is output to the
conversion data register.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS5530-ISZR | 功能描述:模數(shù)轉換器 - ADC IC 24-Bit 1-ch Low Noise ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5531 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA |
| CS5531_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA |
| CS5531-AS | 功能描述:模數(shù)轉換器 - ADC 2-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5531-ASR | 功能描述:模數(shù)轉換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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