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參數(shù)資料
| 型號： | CS51220ED16 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 184K |
| 代理商： | CS51220ED16 |
CS51220
http://onsemi.com
10
The block diagram of the soft hiccup circuit is shown in
Figure 5. When overcurrent occurs and the SS is above 2.9 V,
the OC pulses set the OC latch. The output of the OC latch
turns on the OC delay discharge current to ramp down the SS
voltage. This SS discharge ramp down is at a rate of 50
A
while the SS voltage is above 2.8 V. The level between 2.9 V
and 2.8 V is called the hiccup delay discharge voltage. The
time to cross this voltage creates a short delay. This delay is
useful so that a quick transient overcurrent condition can be
controlled and still allow the supply to return immediately to
normal operation. After reaching the hiccup delay discharge
voltage, the SS current is reduced to 5.0
A and the ISET
foldback current is turned on at 15
A. It is the ISET
foldback current that adjusts the ISET level to establish a
new lower ISENSE current limit level. See Figure 6 for
details.
Figure 5. The Block Diagram of the Soft
Hiccup Operation
SS low
CLK
OC
SS
+
–
One Shot
N00C
Reset
Peak COMP
2.9 V
Trig
OC Latch
Delay COMP
2.8 V
SS
Discharge
ON
S
R
Foldback
Q
A circuit monitors the OC pulses. If the OC pulses cease
for 50
s, the NOt–OverCurrent (NOOC) signal is
generated. This NOOC signal resets the OC Latch and
allows the SS capacitor to charge back up allowing the
output to reestablish regulation.
For an equivalent circuit shown in Figure 6, the ISET
current reduces the overcurrent threshold and sets the new
threshold at
VI(SET) + (3.3 * ISET
R1)
R2
(R1
) R2)
VREF
ISET Pin
R1
R2
ISET
Figure 6. The Voltage Divider Used at the ISET
Pin Allows the ISET Foldback Current to
Reduce the Overcurrent Threshold
The NOOC or SS low (VSS < 0.3 V) signal can reset OC
latch at any time. This event turns off ISET foldback and
allows the recharging of the SS capacitor. Therefore, the IC
allows the power supply to restart periodically or after the
overcurrent condition is cleared. The OC latch can not be set
until the SS capacitor is fully charged.
To implement “hard hiccup” which disables the VO
completely when the SS voltage is ramping down, select a
resistor value greater than 3.3 V/ISET for R1 in Figure 6, and
saturate the internal ISET current source. Since the saturation
voltage is less than the DC shift applied to the ISENSE signal,
the OC comparator output is always high and in turn keeps
the VO low. Figure 7 demonstrates the interactions among
the voltage of SS, ISET and internal signal OC. Figure 8
further describes the specifications associated with the soft
hiccup. The ratio among the charge time, delay time and
discharge time is given at the bottom of Figure 8.
SS
ISET
OC
50
s
2.9 V
2.8 V
0.3 V
Figure 7. Illustrative Waveforms of the
Soft Hiccup Operation
Charge Voltage
Charge
Current
Figure 8. The SS Pin Voltage Under Ramp
Up and Overcurrent Condition and
Associated Specifications.
26
Discharge Voltage
OC Delay
Dischage
Current
Dischage
Current
1
250
Hiccup Delay
Discharge Voltage
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