參數(shù)資料
型號: CS42L51-CNZ
廠商: Cirrus Logic Inc
文件頁數(shù): 41/43頁
文件大小: 0K
描述: IC CODEC STEREO W/HDPN AMP 32QFN
標準包裝: 60
類型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動態(tài)范圍,標準 ADC / DAC (db): 98 / 98
電壓 - 電源,模擬: 1.8V,2.5V
電壓 - 電源,數(shù)字: 1.8V,2.5V
工作溫度: -10°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-QFP
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(5x5)
包裝: 管件
產(chǎn)品目錄頁面: 754 (CN2011-ZH PDF)
配用: 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱: 598-1045
DS679F1
7
CS42L51
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
Pin Name
#
Pin Description
LRCK
1
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SDA/CDIN
(MCLKDIV2)
2
Serial Control Data (Input/Output) - SDA is a data I/O in IC Mode. CDIN is the input data line for the
control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
SCL/CCLK
(IS/LJ)
3
Serial Control Port Clock (Input) - Serial clock for the serial control port.
Interface Format Selection (Input) - Hardware Mode: Selects between IS & Left-Justified interface for-
mats for the ADC & DAC.
AD0/CS
(DEM)
4
Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC Mode; CS
is the chip-select signal for SPI format.
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.
VA_HP
5
Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.
FLYP
6
Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
GND_HP
7
Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.
FLYN
8
Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
VSS_HP
9
Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-
phone section.
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CS42L51
VD
DGND
SDO
U
T
(M/S
)
MCLK
SDIN
SC
L
K
V
SS_HP
AO
UT
B
AO
UTA
VA
AG
ND
DAC_F
ILT+
ADC_F
ILT+
VQ
SDA/CDIN (MCLKDIV2)
SCL/CCLK (IS/LJ)
ADO/CS (DEM)
FLYP
VL
RE
SET
GND_HP
FLYN
AFILTA
AIN1A
AIN1B
AIN2A
AIN2B/BIAS
MICIN1/AIN3A
MICIN2/BIAS/AIN3B
AFILTB
VA_HP
LRCK
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