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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | CS42L51-CNZ |
| 寤犲晢锛� | Cirrus Logic Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 16/43闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CODEC STEREO W/HDPN AMP 32QFN |
| 妯欐簴鍖呰锛� | 60 |
| 椤炲瀷锛� | 绔嬮珨鑱查煶闋� |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | PCM 闊抽牷鎺ュ彛 |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 24 b |
| ADC / DAC 鏁�(sh霉)閲忥細 | 2 / 2 |
| 涓夎绌嶅垎瑾�(di脿o)璁婏細 | 鏄� |
| 鍕曟厠(t脿i)鑼冨湇锛屾婧� ADC / DAC (db)锛� | 98 / 98 |
| 闆诲 - 闆绘簮锛屾ā鎿細 | 1.8V锛�2.5V |
| 闆诲 - 闆绘簮锛屾暩(sh霉)瀛楋細 | 1.8V锛�2.5V |
| 宸ヤ綔婧害锛� | -10°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 32-QFP |
| 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 32-QFN 瑁搁湶鐒婄洡锛�5x5锛� |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 754 (CN2011-ZH PDF) |
| 閰嶇敤锛� | 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC |
| 鍏跺畠鍚嶇ū锛� | 598-1045 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�鐣跺墠绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�
DS679F1
23
CS42L51
SWITCHING CHARACTERISTICS - SPI CONTROL PORT
(Inputs: Logic 0 = DGND, Logic 1 = VL)
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For fsck <1 MHz.
Parameter
Symbol
Min
Max
Units
CCLK Clock Frequency
fsck
06.0
MHz
RESET Rising Edge to CS Falling
tsrs
20
-
ns
CS Falling to CCLK Edge
tcss
20
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
tdh
15
-
ns
Rise Time of CCLK and CDIN
tr2
-100
ns
Fall Time of CCLK and CDIN
tf2
-100
ns
CS
CCLK
CDIN
RST
t
srs
t
scl
t
sch
t
css
t
r2
t
f2
t
csh
t
dsu
t
dh
Figure 7. Control Port Timing - SPI Format
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| CS42L51-CNZR | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC LV Stereo Codec F/Digital Audio Apps RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| CS42L51-DNZ | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC LV Stereo Codec F/ Digital Audio Apps RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| CS42L51-DNZR | 鍔熻兘鎻忚堪:鎺ュ彛鈥擟ODEC IC LV Stereo Codec F Digital Audio Apps RoHS:鍚� 鍒堕€犲晢:Texas Instruments 椤炲瀷: 鍒嗚鲸鐜�: 杞�(zhu菐n)鎻涢€熺巼:48 kSPs 鎺ュ彛椤炲瀷:I2C ADC 鏁�(sh霉)閲�:2 DAC 鏁�(sh霉)閲�:4 宸ヤ綔闆绘簮闆诲:1.8 V, 2.1 V, 2.3 V to 5.5 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:DSBGA-81 灏佽:Reel |
| CS42L52 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
| CS42L52_08 | 鍒堕€犲晢:CIRRUS 鍒堕€犲晢鍏ㄧū:Cirrus Logic 鍔熻兘鎻忚堪:2Low-power, Stereo CODEC w/ Headphone & Speaker Amps |
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