參數(shù)資料
型號(hào): CS42L51-CNZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 35/43頁(yè)
文件大?。?/td> 0K
描述: IC CODEC STEREO W/HDPN AMP 32QFN
標(biāo)準(zhǔn)包裝: 60
類(lèi)型: 立體聲音頻
數(shù)據(jù)接口: PCM 音頻接口
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 98 / 98
電壓 - 電源,模擬: 1.8V,2.5V
電壓 - 電源,數(shù)字: 1.8V,2.5V
工作溫度: -10°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 32-QFP
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 754 (CN2011-ZH PDF)
配用: 598-1005-ND - BOARD EVAL FOR CS42L51 CODEC
其它名稱(chēng): 598-1045
40
DS679F1
CS42L51
4.5.3
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-
out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-
ance state, allowing another device to transmit serial port data without bus contention.
4.5.4
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
4.6
Digital Interface Formats
The serial port operates in standard IS, Left-Justified or Right-Justified (DAC only) digital interface formats
with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the rising edge of
SCLK. Figures 19-21 illustrate the general structure of each format. Refer to “Switching Specifications - Se-
rial Port” on page 20 for exact timing relationship between clocks and data.
Software
Control:
Hardware
Control:
Pin
Setting
Selection
“IS/LJ” pin 3
LO
Left-Justified Interface
HI
IS Interface
CS42L51
Transmitting Device #1
Transmitting Device #2
Receiving Device
3ST_SP
SDOUT
SCLK/LRCK
Figure 18. Tri-State Serial Port
LRCK
SCLK
MS B
LS B
MS B
LS B
AOUTA / AINxA
L e ft C h an ne l
R ig h t C han ne l
SDIN
AOUTB / AINxB
MSB
Figure 19. IS Format
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