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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 84/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5 |
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84
vice serves as a bus master. The clock low time
and high time are defined as follows:
t
SCLl
= t
SCLh
= 2*SCLFRQ*t
CLK
Where t
CLK
is this device’s clock cycle when in
Active mode.
SCLFRQ may be programmed to values in the
range of 0001000
2
(8
10
) through 1111111
2
(127
10
). Using any other value has unpredict-
able results.
19.3.6
ACB Own Address Register (ACBADDR) is a byte-wide,
read/write register that holds the module’s ACCESS.bus ad-
dress. Reset value is undefined.
7
ACB Own Address Register (ACBADDR)
ADDR
Own Address. Holds the 7-bit ACCESS.bus
address of this device. When in slave mode,
the first seven bits received after a Start Condi-
tion are compared to this field (first bit received
to bit-6, and the last to bit-0). If the address field
matches the received data and SAEN is set, a
match is declared.
Slave Address Enable. When set SAEN indi-
cates that the ADDR field holds a valid address
and enables the match of ADDR to an incom-
ing address byte. When cleared, the ACB does
not check for an address match.
SAEN
19.4
1. When the ACB is disabled the ACBCST.BB bit is
cleared. After enabling the ACB (ACBCTL2.ENABLE is
set to 1) in systems with more then one master, the bus
may be in the middle of a transaction with another de-
vice, which is not reflected by BB.
USAGE HINTS
There is a need to allow the ACB to synchronize to the
bus activity status before issuing a request to become
the bus master, to prevent bus errors. Thus, before issu-
ing a request to become the bus master for the first time,
the software should check that there is no activity on the
bus by checking the BB bit after the bus allowed time-out
period.
2. When waking up from power down, before checking
ACBCST.MATCH, use ACBCST.BUSY to make sure
that the address transaction is over.
3. The BB bit is intended to solve a deadlock in which two,
or more, devices detect a usage conflict on the bus and
both devices cease being bus masters at the same time.
In this situation, the BB bits of both devices are active
(because each deduces that there is another master
currently performing a transaction, while in fact no de-
vice is executing a transaction), and the bus would stay
locked until some device sends a ACBCTL1.STOP con-
dition.
The ACBCST.BB bit allows the software to monitor bus
usage, so it can avoid sending a STOP signal in the mid-
dle of the transaction of some other device on the bus.
This bit detects whether the bus remains unused over a
certain period, while the BB bit is set.
4. In some cases the bus may get stuck with the SCL and/
or SDA lines active. A possible cause to this is an erro-
neous Start or Stop Conditions that occur in the middle
of a slave receive session.
When the SCL line is stuck active, there is nothing that
can be done, and it is the responsibility of the module
that holds the bus to release it.
In case of SDA line is stuck active, the ACB module en-
able the release of the bus by using the following se-
quence. Note that in normal cases SCL may be toggled
only by the bus master. This protocol is a recovery
scheme which is an exception that should be used only
in the case where there is no other master on the bus.
The recovery scheme is as follows:
a. Disable and re-enable the module to set it into the
not addressed slave mode.
b Set the ACBCTL1.START bit to make an attempt to
issue a Start Condition.
c. Check if the SDA line is active (low) by reading
ACBCST.TSDA bit. If it is active, issue a single SCL
cycle by writing 1 to ACBCST.TGSCL bit. If the SDA
line is not active, continue from step ‘e’.
d. Check if ACBST.MASTER is set, which indicates
that the Start Condition was sent. If not, repeat step
c and d until the SDA is released.
e. Clear the BB bit. This enables the START bit to be
executed. Continue according to “Bus Idle Error Re-
covery” on page 81.
6
0
SAEN
ADDR
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