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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 60/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5 |
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value held in the period register. In that case the counter will
count up to FF
16
and then roll over to 00
16
. In any case the
TIOx pin always changes its state at the 00
16
to 01
16
transi-
tion of the counter.
The user software may only write to the COUNTx register if
both TxRUN bits of a timer subsystem are cleared. Any
writes to the counter register while either timer is running will
be ignored.
The two I/O pins associated with a timer subsystem function
as independent PWM outputs in the dual 8-bit PWM mode. If
a PWM timer is stopped via its associated MODE.TxRUN bit
the following actions result:
— The associated TIOx pin will return to its default value
as defined by the IOxCTL.PxPOL bit.
— The counter will stop and will retain its last value.
— Any pending updates of the PERCAPx and DTYCAPx
register will be completed.
— The prescaler counter will be stopped and reset if both
MODE.TxRUN bits are cleared.
Figure 20 illustrates the configuration of a timer subsystem
while operating in dual 8-bit PWM mode. The numbering in
Figure 20 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
16.1.2
Each of the four timer subsystems may be independently
configured to provide a single 16-bit PWM channel. In this
case the lower and upper bytes of the counter are concate-
nated to form a single 16-bit counter.
Operation in 16-bit PWM mode is conceptually identical to
the dual 8-bit PWM operation as outlined under Dual 8-bit
PWM Mode on page 59. The 16-bit timer may be started or
stopped with the lower MODE.TxRUN bit, i.e. T1RUN for tim-
er subsystem 1.
The two TIOx outputs associated with a timer subsystem can
be used to produce either two identical PWM waveforms or
two PWM waveforms of opposite polarities. This can be ac-
complished by setting the two PxPOL bits of the respective
timer subsystem to either identical or opposite values.
16-Bit PWM Mode
Figure 21 illustrates the configuration of a timer subsystem
while operating in 16-bit PWM mode. The numbering in
Figure 21 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
Figure 21.
VTU 16-bit PWM Mode
16.1.3
In addition to the two PWM modes, each timer subsystem
may be configured to operate in an input capture mode which
provides two 16-bit capture channels. The input capture
mode can be used to precisely measure the period and duty
cycle of external signals.
In capture mode the counter COUNTx operates as a 16-bit
up-counter while the two TIOx pins associated with a timer
subsystem operate as capture inputs. A capture event on the
TIOx pins causes the contents of the counter register
(COUNTx) to be copied to the PERCAPx or DTYCAPx regis-
ters respectively.
Starting the counter is identical to the 16-bit PWM mode, i.e.
setting the lower of the two MODE.TxRUN bits will start the
counter and the clock prescaler. In addition, the capture
event inputs are enabled once the MODE.TxRUN bit is set.
The TIOx capture inputs can be independently configured to
detect a capture event on either a positive transition, a neg-
ative transition or both a positive and a negative transition. In
addition, any capture event may be used to reset the counter
COUNTx and the clock prescaler counter. This avoids the
need for the user software to keep track of timer overflow
conditions and greatly simplifies the direct frequency and
duty cycle measurement of an external signal.
Figure 22 illustrates the configuration of a timer subsystem
while operating in capture mode. The numbering in Figure 22
Dual 16-Bit Capture Mode
Counter
C1PRSC
==
COUNT1[15:8]
PERCAP1[15:8]
DTYCAP1[15:8]
TIO2
compare
compare
0
7
8
15
COUNT1[7:0]
PERCAP1[7:0]
DTYCAP1[7:0]
compare
compare
0
7
[7:0]
[15:8]
S
R
Q
P2POL
TIO1
S
R
Q
P1POL
T1RUN
T2RUN
Res
Res
TMOD1=01
Figure 20.
VTU Dual 8-bit PWM Mode
Counter
C1PRSC
==
COUNT1[15:0]
PERCAP1[15:0]
DTYCAP1[15:0]
TIO2
compare
compare
0
7
0
15
[15:0]
S
R
Q
P2POL
TIO1
S
R
Q
P1POL
T1RUN
Restart
TMOD1=10
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