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| 型號(hào)： | COMMPROCWP |
| 英文描述： | Communications Processors: A Definition and Comparison |
| 中文描述： | 通訊處理器：定義和比較 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 413K |
| 代理商： | COMMPROCWP |
May 3, 2000
Network System Design Alternatives
7
Pattern Matching Processors
Another approach at providing programmability is a further
extension of the single-function component. Examples of
this include “pattern matching processors” that focus on
providing configurable classification engines (see Figure 6).
Figure6
Typical Pattern Processor Design (OC-12 WAN Interface)
Pattern matching processors provide more flexibility and
configurability than the fixed-function devices described
above, even allowing support for multiple protocol types
(ATM, IP and so on). The value of these devices is in
embedded algorithms specifically useful for classification,
which are sometimes configurable through a proprietary
programming language.
Aside from the obvious issues with proprietary languages, it
is often difficult to evaluate the performance of these
processors within an overall system design, due to the
performance links between the classification functions and
the switching and routing functions that must be
implemented elsewhere in the design.
Network Processor Chip Sets
One of the fastest growing areas of merchant
communications silicon is in the area of switching chipsets.
Many ATM switching platforms are based on standard
silicon, as are most low-end Ethernet workgroup switches.
For the low-end systems, the obvious benefits are
the ability
to develop commodity-oriented products quickly and at
very low cost. While at the high-end, systems are often built
with a mixture of the standard components that make up
the chipset and custom designs (usually ASICs) that provide
vendor differentiation.
Host CPU
Subsystem
Host CPU
Memory
Bus
Interface
Framer
SRAM
Multi-MB
SRAM or
SDRAM
Lookup Memory
Control Memory
Pattern
Matching
Processor
Routing/
Switching
Engine
Fabric
Interface
ASIC
Interface
Comversion
ASIC
PCI Bus
SDRAM Bus
SDRAM
Packet Memory
Fabric
OC-12
Port
Among the high-end switching chipsets are the early
“network processors” offering a complete fabric and packet
processing solution for systems ranging up to multi-gigabit
performance. Some of these architectures support both
packet and cell-oriented systems, though not at the same
time. Additionally, there may be fixed, limited interfaces
within the architecture that enable networking vendors to
program a small amount of functionality, or pass data to an
external device (usually of custom design).
A key drawback of the “switch-on-a-chip” and network
processor designs is the limited flexibility for providing
system differentiation or additional services beyond those
envisioned by the original silicon architects. Invariably, the
instruction sets provided in the architecture are proprietary,
primitive, and have limited tool support. It is not
uncommon for designers to discover the performance and
functional limitations of these interfaces late in the design
cycle, forcing time-to-market delays and critical functional
trade-offs.
Most of these solutions also use proprietary interconnects
between the various chipset components, from port
processing through switching fabric. Not only does this limit
the ability of the networking vendor to choose
“best-in-class” solutions, but the silicon architecture tends
to “blur the lines” between functions. The end result is
limited scalability of the final product, preventing future
growth and adaptability of the product line. Such an “all or
nothing” approach to system design can often be difficult
for networking vendors to accept for strategic product lines.
For commodity-oriented communication products,
complete “switch-on-chip” solutions can be viable
time-to-market approaches. However, for higher-end
products that must live in a complex and evolving
application environment, an open approach (from both
hardware and software perspectives) is required.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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