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| 型號(hào)： | COMMPROCWP |
| 英文描述： | Communications Processors: A Definition and Comparison |
| 中文描述： | 通訊處理器：定義和比較 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 413K |
| 代理商： | COMMPROCWP |
May 3, 2000
Network Processors: Universal Programmability and Performance
3
Simple Programming Model
The programmability of a Network Processor must be
readily accessible to the developer in order to be useful. By
far the most common software languages in real-time
communications systems are C and C++, with millions of
skilled programmers and many more lines of existing code.
Programming in the C and C++ languages also enhances
the future portability of the code-base, enabling use in
future generations of Network Processors and industry
standard programming interfaces. This is not possible with
specialized languages or state-machine codes.
Maximum System Flexibility
True Network Processors integrate all the functions
implemented between the physical interfaces and the
switching fabric, enabling an open approach for the PHY
and fabric levels. This permits best-of-breed, multi-vendor
solutions that allow vendors to offer true product
differentiation and scalability. In addition, software
implementation of these functions allows simpler upgrade
paths in this constantly changing networking world.
Massive Processing Power
The architecture of the Network Processor needs to be more
than the amalgamation of a few RISC core processors and
some packet processing state machines. A fully optimized
processing architecture, with a high MIPs (millions of
instructions per second) to Gbps (Gigabits per second) ratio
is required to support wire-speed operation at high
bandwidths and still have processing headroom for
advanced applications.
High Functional Integration
Network Processors need to provide a high level of system
integration that dramatically reduces part count and system
complexity, while simultaneously improving performance,
as compared to using a design that incorporates multiple
components (such as ASSPs).
In addition, a highly integrated Network Processor avoids
the interconnection bottlenecks common with component
oriented designs. Integrated coprocessor engines (such as
for classification or queuing) can be fully utilized by internal
processing units without interconnection penalties.
Integration of lower layer functions (such as SONET framers)
within the chip also enables higher port densities and lower
costs than have typically been possible in the past.
Figure 3 and Figure 4 provide a comparison of a multiple
component system versus a highly-integrated system.
Figure 3
Typical Interworking Design Using ASSPs and CPU
Figure 4
Interworking Design Using a Highly Integrated Network
Processor
Stable Programming Interfaces
A communication processor cannot deliver on software
flexibility and portability if the programming interfaces are
dependent on the processor. The processor’s architecture
must support generic “Communications Programming
Interfaces” to simplify the programming task and allow
future software reuse across generations of the processor.
By delivering software stability across product generations,
Network Processors radically improve software
development cycles and reliability. Software reliability is the
largest factor in total system availability.
Third-Party Support
To realize the full potential of a software-driven
environment, the Network Processor needs to be the
foundation of a complete communications platform that
takes advantage of industry-wide hardware extensions,
ATM
Port
Memory
Memory
Memory
AAL5
SAR
AAL5
SAR
System
Control
CPU
HDLC
Controller
T-Carrier
Framers
x N
PCI
Bus
Memory
HDLC
Controller
T-Carrier
Framers
Memory
ATM
Port
Memories
AAL5 SAR
Single Network Processor
FRF/ATM/IP
Interworking
PCI Bus
T-Carrier
Framers
x N
60Gbps
T-Carrier
Framers
Fabric
Mgmt
System
Control
HDLC
Controller
Table lookups,
Queuing,
Memory Mgmt
HDLC
Controller
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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