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| 型號： | COMMPROCWP |
| 英文描述： | Communications Processors: A Definition and Comparison |
| 中文描述： | 通訊處理器：定義和比較 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 413K |
| 代理商： | COMMPROCWP |
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software applications, and tool suites. This is only possible
with an architecture that has the flexibility to support
virtually any third-party protocol stack, any PHY or fabric
interface, and links with industry standard tools. Such broad
support significantly decreases time-to-market.
Network System Design Alternatives
Of course, before the Network Processor there were a
number of design alternatives that in their own ways
provided some assistance in building better networking
products. From using completely hard-wired solutions to
configurable processors, and more recently, network
processor chipsets, networking vendors have incrementally
improved and evolved their designs, but not without major
compromises.
Custom ASIC Designs
Until recently, common practice of high-speed networking
design has involved the development of custom ASICs for
critical elements of the architecture. This approach has been
dictated by the requirement for “wire-speed” performance
at reasonable cost.
Most vendors have had limited success in leveraging an
ASIC or ASIC family into multiple product lines, preventing
them from amortizing the development costs across a
broad range of revenue-generating products.
Implementing product architectures in ASICs is a high-cost
proposition from a number of perspectives:
The design cycle is typically 18 months (and can extend
beyond 3 years). Projecting market requirements that far
in advance is difficult given the competitive dynamics of
the market, resulting in the same company needing to
place “multiple bets” to assure market success.
The risk of design failures in ASIC-based development is
large, given the many months that are often required to
correct design flaws (due to the lack of flexibility present
in hardware-based designs).
The limited flexibility of hardware-based designs
severely limits the ability to adjust product functionality
to evolving market demands before and after market
introduction. The result is shorter product lifecycles and
greater to-market risks.
ASIC design expertise is a rare commodity. The ability to
hire and retain talented designers has become a
fundamental limit to the rate of product development
for many vendors.
The design tools for complex ASICs can run in the
millions of dollars (ASIC emulators, for instance) and
require constant refresh as the technology advances.
Perhaps the largest, and often hidden cost, is the need to
re-architect and re-write critical software associated with
each product generation. Frequently, the extent of the
re-write is unforeseen and prescribed by the need to
optimize the designs around the hardware and ASIC
technology, rather than around software re-use. Thus
regardless of how much key functionality is embedded
in the hardware, a massive amount of “slow-path”
software is generally still required.
Additionally, the large opportunity cost of software
re-writes often prevents vendors from delivering the
value-added services and applications that provide true
market differentiation.
While there remains a set of products that will require the
customization available from ASICs, most vendors are eager
to move to design alternatives that will improve their
time-to-market and reduce development risks.
Customizable ASICs and Configurable Processor
Designs
Several new design technologies are emerging to address
some of the issues and risks of ASIC-based designs. These
include:
Integrated Circuits (ICs) incorporating fixed-function
network logic blocks with configurable interconnects
(sometimes termed “systems-on-a-chip”)
Configurable processor cores with changeable
instruction sets that allow limited modifications to
accomplish some network-specific tasks
Configurable “Systems-on-a-Chip”
Configurable “system-on-a-chip” approaches mix a number
of fixed-function blocks, perhaps including a CPU-core, on a
single chip with FPGA-like configurable interconnects.
These devices speed-up the development cycle by enabling
designers to choose from a “menu” of available functions
that they assemble to build the desired part. Such devices
sometimes promise future field re-configurability of the
interconnection between different elements.
While this approach offers some time-to-market
advantages compared to traditional ASICs, having a
collection of fixed-function blocks limits the flexibility to
adapt to new features and standards because the design
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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