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| 型號： | COMMPROCWP |
| 英文描述： | Communications Processors: A Definition and Comparison |
| 中文描述： | 通訊處理器：定義和比較 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 413K |
| 代理商： | COMMPROCWP |
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Some vendors have proposed using DSPs (or multiple DSP
cores on a single chip) to expand beyond pure signal
processing into higher-level protocol handling. While some
protocol processing may be supported within DSP
architectures, the basic tasks of data formatting, parsing,
classification, modification, and switching are
fundamentally different from the mathematically oriented
tasks of DSPs.
The tools for programming DSPs are also oriented toward
algorithmic implementations and require specialized
language support. So, while DSPs are a great example of the
power of programmability within communications systems,
they are not an adequate universal processing solution for
the higher-level protocol processing functions.
Configurable State Machine Engines
Another approach for achieving flexibility at the component
level is the application of configurable state machine
engines for off-loading some of the protocol processing
from general purpose CPUs.
These devices have sometimes been classified as “network
processors” although they do not execute any “software” in
the traditional sense. Instead, they have a series of
configurable state machines that perform some of the
framing, data parsing, and classification functions. Based on
the configuration, these devices may pre-process ATM,
Frame Relay, or Ethernet formatted data for a
general-purpose CPU, for additional components (such as a
MAC, classification engine, or custom ASIC), or for both.
Figure 5 shows a product design using a configurable state
machine engine.
Figure5
Typical State Machine Engine-Based Design
Framers
CAM
SDRAM
SRAM
Host CPU
Subsystem
FPGA
Fabric
Interface
ASIC
Bus
Interface
Packet Processing
State Machine
Engine
Interface
Conversion
ASIC
Host CPU
Memory
Packet Memory
The state machines are configured through CPU-accessible
registers or external devices (such as FPGAs). Because the
configuration of state machines can be quite complex,
some vendors implement the required functions using
specialized procedural languages to generate the actual
state machine code; while other vendors provide a suite of
pre-configured codes for a variety of ‘canned’ applications.
Although these state-machine-oriented devices offer more
flexibility than typical fixed-function ASSPs, they suffer from
the same architectural limitations. The design must still
revolve around a general-purpose CPU or a custom ASIC in
the switching path, with the requisite performance,
flexibility, and time-to-market trade-offs.
Programmable Special Purpose Devices
Some communication component vendors have focused on
increasing the programmability of their single-function
components in order to provide better future adaptability
and to broaden the market appeal of their devices.
An example is segmentation and reassembly (SAR) devices,
designed specifically to perform the interworking between
frame-based (Ethernet and IP) networks and ATM-based
networks. SAR architectures typically consist of Utopia
interfaces, frame and cell parsing logic, dedicated
scheduling and queuing support, and a custom processor
for implementing the interworking protocols. A software-
oriented processor is attractive in SAR components due to
the rapidly evolving ATM interworking standards.
Vendors of other components, such as HDLC controllers, are
also allowing the “extra” processing cycles within their
devices to be used for customer-defined applications.
There are many difficulties when applying these devices
beyond their originally intended purpose (SARing, HDLC
multiplexing, and so on). For example, it can be difficult to
determine exactly how many “extra” cycles are really
available for custom processing. Further, The internal
processors themselves are typically proprietary CPUs,
specifically designed for one function. This means
questionable suitability to more general processing tasks,
often surprisingly large impacts on system performance,
and the possible immaturity of the programming tools.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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