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CHRONTEL
Table 1: Pin Description
CH7009A
4
201-0000-035 Rev 1.1, 5/8/2000
64-Pin
LQFP
14
# Pins
Type
Symbol
Description
1
In/Out
SD
Serial Data Input / Output
This pin functions as the serial data pin of the IIC interface
port, and uses the DVDD supply.
Serial Clock Input
This pin functions as the clock pin of the IIC interface port,
and uses the DVDD supply.
TMDS
TM
Link Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm
resistor should be connected between this pin and TGND using
short and wide traces.
TMDS
TM
Data Channel 0 Outputs
These pins provide the DVI differential outputs for data
channel 0 (blue).
TMDS
TM
Data Channel 1 Outputs
These pins provide the DVI differential outputs for data
channel 1 (green).
TMDS
TM
Data Channel 2 Outputs
These pins provide the DVI differential outputs for data
channel 2 (red).
TMDS
TM
Link Clock Outputs
These pins provide the differential clock output for the DVI
interface corresponding to data on the TDC[0:2] outputs.
Current Set Resistor Input
This pin sets the DAC current. A 140 ohm resistor should be
connected between this pin and GND (DAC ground) using
short and wide traces.
Composite Video
This pin outputs a composite video signal capable of driving a
75 ohm doubly terminated load.
Luma / Green Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be s-video luminance or green
.
Chroma / Red Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be s-video chrominance or red.
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The
output can be selected to be composite video or blue.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XO. However, an external
clock can drive the XI/FIN input.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XI / FIN. However, if an
external CMOS clock is attached to XI/FIN, XO should be left
open.
15
1
In
SC
19
1
In
VSWING
22, 21
2
Out
TDC0,
TDC0*
25, 24
2
Out
TDC1,
TDC1*
28, 27
2
Out
TDC2,
TDC2*
30, 31
2
Out
TLC,
TLC*
35
1
In
ISET
36
1
Out
CVBS
37
1
Out
Y/G
38
1
Out
C/R
39
1
Out
CVBS/B
42
1
In
XI / FIN
43
1
In
XO