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201-0000-035 Rev 1.1, 5/8/2000
37
CHRONTEL
CH7009A
Bit 5 of register CD can be read at any time to determine the level of the hot plug detect pin. When the hot plug
detect pin changes state, and the DVI output is selected, the P-OUT / TLDET* output pin will be pulled low
signifying a change in the DVI termination. At this point, the HPIR bit in register 1Eh should be set high, then low
to reset the hot plug detect circuit.
Bit 6 of register CD contains the MSB value for the crystal oscillator adjustment. This control is described in detail
in the DC register description (register 21h).
Bit 7 of register CD enables the hot plug interrupt detection signal output from the GPIO[1] pin. A value of ‘1’
allows the hot plug detect circuit to pull the GPIO[1] / TLDET* pin low when a change of state has taken place on
the hot plug detect pin. A value of ‘0’ disables the interrupt signal. The GOENB1 control bit in register 1Eh should
be set to ‘1’ when HPIE2 is set to ‘1’.
DAC Control Register
Symbol:
Address:
Bits:
DC
21h
6
Bit 0 of register DC selects the DAC bypass mode. A value of ‘1’ outputs the incoming data directly at the
DAC[2:0] outputs.
Bits 2-1 of register DC control the DAC gain. DACG0 should be set low for NTSC and PAL-M video standards,
and high for PAL and NTSC-J video standards. DACG1 should be low when the input data format is RGB (IDF =
0-3), and high when the input data format is YCrCb (IDF = 4).
Bits 4-3 of register DC select the signal to be output from the C/H Sync pin according to
Table 19
below.
Bits 7-6 of register DC controls the crystal oscillator. The default value is recommended.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
XOSC1
R/W
XOSC0
R/W
SYNCO1 SYNCO0
R/W
0
DACG1
R/W
DACG0
R/W
DACBP
R/W
R/W
0
0
0
0
0
0
Table 19: Composite / Horizontal Sync Output
SYNCO[1:0]
C/H Sync Output
00
No Output
01
VGA Horizontal Sync
10
TV Composite Sync
11
TV Horizontal Sync