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參數(shù)資料
| 型號： | CAT93C57WI-1.8-T3REVE |
| 元件分類： | PROM |
| 英文描述： | 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, MS-012, SOIC-8 |
| 文件頁數(shù)： | 16/18頁 |
| 文件大?。?/td> | 246K |
| 代理商： | CAT93C57WI-1.8-T3REVE |
CAT93C56, CAT93C57
Catalyst Semiconductor, Inc.
7
Doc. No. MD-1088 Rev. Q
Characteristics subject to change without notice
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the
CAT93C56/57 will come out of the high impedance
state and, after sending an initial dummy zero bit, will
begin shifting out the data addressed (MSB first). The
output data bits will toggle on the rising edge of the
SK clock and are stable after the specified time delay
(tPD0 or tPD1).
For the CAT93C56/57, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will auto-
matically increment to the next address and shift out
the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues
to toggle, the device will keep incrementing to the next
address automatically until it reaches to the end of the
address space, then loops back to address 0. In the
sequential READ mode, only the initial data word is
preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit. The READ
instruction timing is illustrated in Figure 2.
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power-up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable)
instruction.
Once
the write
instruction is enabled, it will remain enabled until power
to the device is removed, or the EWDS instruction is
sent. The EWDS instruction can be used to disable all
CAT93C56/57 write and erase instructions, and will
prevent any accidental writing or clearing of the device.
Data can be read normally from the device regardless of
the write enable/disable status. The EWEN and EWDS
instructions timing is shown in Figure 3.
Figure 2. READ Instruction Timing
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
DI
DO
HIGH-Z
11
0
AN AN–1
A0
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Don't Care
tPD0
CS
DI
STANDBY
10
0
*
* ENABLE = 11
DISABLE = 00
SK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT93C57WI-GT2E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WI-GT3E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WIT2E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WIT3E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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