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參數(shù)資料
| 型號： | CAT93C57WI-1.8-T3REVE |
| 元件分類： | PROM |
| 英文描述： | 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, MS-012, SOIC-8 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 246K |
| 代理商： | CAT93C57WI-1.8-T3REVE |
CAT93C56, CAT93C57
Doc. No. MD-1088 Rev. Q
4
Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
(1), CAT93C56, Die Rev. G – New Product
VCC = +1.8V to +5.5V, TA = -40°C to +125°C, unless otherwise specified.
Limits
Symbol
Parameter
Min
Max
Units
tCSS
CS Setup Time
50
ns
tCSH
CS Hold Time
0
ns
tDIS
DI Setup Time
100
ns
tDIH
DI Hold Time
100
ns
tPD1
Output Delay to 1
0.25
s
tPD0
Output Delay to 0
0.25
s
tHZ
(2)
Output Delay to High-Z
100
ns
tEW
Program/Erase Pulse Width
5
ms
tCSMIN
Minimum CS Low Time
0.25
s
tSKHI
Minimum SK High Time
0.25
s
tSKLOW
Minimum SK Low Time
0.25
s
tSV
Output Delay to Status Valid
0.25
s
SKMAX
Maximum Clock Frequency
DC
2000
kHz
A.C. CHARACTERISTICS
(1), CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E - NOT RECOMMENDED FOR NEW DESIGNS)
Limits
VCC = 1.8V - 5.5V
VCC = 2.5V - 5.5V
VCC = 4.5V - 5.5V
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
ns
tDIS
DI Setup Time
400
200
100
ns
tDIH
DI Hold Time
400
200
100
ns
tPD1
Output Delay to 1
1
0.5
0.25
s
tPD0
Output Delay to 0
1
0.5
0.25
s
tHZ
(2)
Output Delay to High-Z
400
200
100
ns
tEW
Program/Erase Pulse Width
10
ms
tCSMIN
Minimum CS Low Time
1
0.5
0.25
s
tSKHI
Minimum SK High Time
1
0.5
0.25
s
tSKLOW
Minimum SK Low Time
1
0.5
0.25
s
tSV
Output Delay to Status Valid
1
0.5
0.25
s
SKMAX
Maximum Clock Frequency
DC
250
DC
500
DC
1000
kHz
Notes
:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
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