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參數(shù)資料
| 型號： | CAT93C57WI-1.8-T3REVE |
| 元件分類： | PROM |
| 英文描述： | 128 X 16 MICROWIRE BUS SERIAL EEPROM, PDSO8 |
| 封裝： | 0.150 INCH, GREEN, MS-012, SOIC-8 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 246K |
| 代理商： | CAT93C57WI-1.8-T3REVE |
CAT93C56, CAT93C57
Catalyst Semiconductor, Inc.
5
Doc. No. MD-1088 Rev. Q
Characteristics subject to change without notice
POWER-UP TIMING
(1) (2)
Symbol
Parameter
Max
Units
tPUR
Power-up to Read Operation
1
ms
tPUW
Power-up to Write Operation
1
ms
Notes
:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. Test Conditions
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.4V to 2.4V
4.5V ≤ VCC ≤ 5.5V
Timing Reference Voltages
0.8V, 2.0V
4.5V ≤ VCC ≤ 5.5V
Input Pulse Voltages
0.2VCC to 0.7VCC
1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages
0.5VCC
1.8V ≤ VCC ≤ 4.5V
Output Load
Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C56/57 can be organized as
either registers of 16 bits or 8 bits. When organized as
X16, seven 10-bit instructions for 93C57 or seven 11-
bit instructions for 93C56 control the reading, writing
and erase operations of the device. When organized
as X8, seven 11-bit instructions for 93C57 or seven
12-bit instructions for 93C56 control the reading,
writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and
will generate on chip, the high voltage required during
any write operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The serial communication protocol follows the timing
shown in Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state
on the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in
applications where the DI pin and the DO pin are to be
tied together to form a common DI/O pin.
Figure 1. Sychronous Data Timing
SK
DI
CS
DO
tDIS
tPD0,tPD1
tCSMIN
tCSS
tDIS
tDIH
tSKHI
tCSH
VALID
DATA VALID
tSKLOW
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CAT93C57WI-GT2E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WI-GT3E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WIT2E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WIT3E | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM |
| CAT93C57WI-TE13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
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