參數(shù)資料
型號(hào): CAT28F102NA-12T
元件分類: PROM
英文描述: 64K X 16 FLASH 12V PROM, 120 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 2/15頁(yè)
文件大小: 107K
代理商: CAT28F102NA-12T
CAT28F102
10
Doc. No. 1014, Rev. A
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Figure 7. Chip Erase Algorithm(1)
28F101-07
START ERASURE
APPLY VPPH
INITIALIZE
ADDRESS
INITIALIZE
PLSCNT = 0
WRITE ERASE
SETUP COMMAND
WRITE ERASE
COMMAND
TIME OUT 10ms
WRITE ERASE
VERIFY COMMAND
TIME OUT 6
s
READ DATA
FROM DEVICE
DATA =
FFH?
LAST
ADDRESS?
WRITE READ
COMMAND
APPLY VPPL
ERASURE
COMPLETED
APPLY VPPL
ERASE
ERROR
INCREMENT
ADDRESS
INC PLSCNT
= 1000 ?
NO
YES
PROGRAM ALL
BYTES TO 0000H
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
BUS
OPERATION COMMAND
COMMENTS
READ
STANDBY
WRITE
STANDBY
ERASE
VERIFY
READ
INITIALIZE ADDRESS
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
PLSCNT = PULSE COUNT
DATA = XX20H
WAIT
ADDRESS = BYTE TO VERIFY
DATA = XXA0H
STOPS ERASE OPERATION
READ BYTE TO
VERIFY ERASURE
DATA = 0000H
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
WRITE
ERASE
WAIT
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
DATA = XX20H
Main Menu
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